Marantz-SR6006v5-avr-sm 电路图维修手册.pdf

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1、Service Manual Some illustrations using in this service manual are slightly different from the actual set. Please use this service manual with referring to the operating instructions without fail. For purposes of improvement, specifications and design are subject to change without notice. AV Surroun

2、d Receiver SR6006 /U1B/N1B/N1SG/K1B SR6006 S0409-1V05DM/DG1111Copyright 2011 D this pad must be robustly connected to GND. 176 W9864G6JH-6(HDMI:IC409) W9864G2IH Publication Release Date: Aug. 28, 2009 - 4 - Revision A03 4. PIN CONFIGURATION 177 W9864G6JH-6Blockdiagram W9864G2IH Publication Release D

3、ate: Aug. 28, 2009 - 6 - Revision A03 6. BLOCK DIAGRAM DQ0 DQ31 DQM03 CLK CKE A10 CLOCK BUFFER COMMAND DECODER ADDRESS BUFFER REFRESH COUNTER COLUMN COUNTER CONTROL SIGNAL GENERATOR MODE REGISTER COLUMN DECODER SENSE AMPLIFIER CELL ARRAY BANK #2 COLUMN DECODER SENSE AMPLIFIER CELL ARRAY BANK #0 COLU

4、MN DECODER SENSE AMPLIFIER CELL ARRAY BANK #3 DATA CONTROL CIRCUIT DQ BUFFER COLUMN DECODER SENSE AMPLIFIER CELL ARRAY BANK #1 ROW DECODER ROW DECODER ROW DECODERROW DECODER A0 A9 BS0 BS1 CS RAS CAS WE 178 W9864G6JH-6Pindescription W9864G2IH Publication Release Date: Aug. 28, 2009 - 5 - Revision A03

5、 5. PIN DESCRIPTION PIN NUMBER PIN NAME FUNCTION DESCRIPTION 24, 25, 26, 27, 60, 61, 62, 63, 64, 65, 66 A0A10 Address Multiplexed pins for row and column address. Row address: A0A10. Column address: A0A7. A10 is sampled during a precharge command to determine if all banks are to be precharged or ban

6、k selected by BS0, BS1. 22, 23 BS0, BS1 Bank Select Select bank to activate during row address latch time, or bank to read/write during address latch time. 2, 4, 5, 7, 8, 10, 11, 13, 31, 33, 34, 36, 37, 39, 40, 42, 45, 47, 48, 50, 51, 53, 54, 56, 74, 76, 77, 79, 80, 82, 83, 85 DQ0DQ31 Data Input/ Ou

7、tput Multiplexed pins for data output and input. 20 CS Chip Select Disable or enable the command decoder. When command decoder is disabled, new command is ignored and previous operation continues. 19 RAS Row Address Strobe Command input. When sampled at the rising edge of the clock RAS , CAS and WE

8、define the operation to be executed. 18 CAS Column Address Strobe Referred to RAS 17 WE Write Enable Referred to RAS 16, 28, 59, 71 DQM0DQM3 Input/Output Mask The output buffer is placed at Hi-Z (with latency of 2) when DQM is sampled high in read cycle. In write cycle, sampling DQM high will block

9、the write operation with zero latency. 68 CLK Clock Inputs System clock used to sample inputs on the rising edge of clock. 67 CKE Clock Enable CKE controls the clock activation and deactivation. When CKE is low, Power Down mode, Suspend mode, or Self Refresh mode is entered. 1, 15, 29, 43 VDD Power

10、Power for input buffers and logic circuit inside DRAM. 44, 58, 72, 86 VSS Ground Ground for input buffers and logic circuit inside DRAM. 3, 9, 35, 41, 49, 55, 75, 81 VDDQ Power for I/O Buffer Separated power from VDD, to improve DQ noise immunity. 6, 12, 32, 38, 46, 52, 78, 84 VSSQ Ground for I/O Bu

11、ffer Separated ground from VSS, to improve DQ noise immunity. 14, 21, 30, 57, 69, 70, 73 NC No Connection No connection. 179 MX29LV160DBTI-70G(HDMI:IC410) MX29LV160DBTI-70GBlockDiagram 180 AK4424ET(HDMI:IC455,IC457) AK4424ET Block Diagram 181 AK5358BET(HDMI:IC451) AK5358BETPinFunction 182 AK4358VQ(H

12、DMI:IC441) AK4358VQPinFunction ASAHI KASEI AK4358 MS0203-J-01 2006/02 - 2 - ? AK4358VQ -40+85C 48pin LQFP AKD4358 評価 ? 配置 LOUT1- ROUT1+ 1 LOUT1+ 48 2 DZF33 DZF24 DZF15 CAD06 ACKSN7 PDN8 BICK9 MCLK10 DVDD ROUT1- 47 LOUT2+ 46 45 44 ROUT2-43 LOUT3+ 42 LOUT3- 41 ROUT3+ 40 ROUT3- 39 LOUT4+ 38 SDTI4 13 SD

13、TI1 14 SDTI2 15 SDTI3 16 LRCK 17 18 CCLK/SCL 19 CDTI/SDA 20 CSN/CAD1 21 DCLK 22 DSDL4 23 36 35 34 33 32 31 30 29 28 27 26 AVSS AVDD VREFH ROUT4+ ROUT4- DIF0 DSDR3 DSDL3 DSDR2 DSDL2 DSDR1 AK4358VQ Top View I2C LOUT2- ROUT2+ LOUT4- 37DSDR4 24 11 DVSS12 25DSDL1 ASAHI KASEI AK4358 MS0203-J-01 2006/02 -

14、4 - PIN/FUNCTION No. Pin Name I/O Function 1 LOUT1- O DAC1 Lch Negative Analog Output Pin 2 LOUT1+ O DAC1 Lch Positive Analog Output Pin 3 DZF3 O Zero Input Detect 3 Pin 4 DZF2 O Zero Input Detect 2 Pin 5 DZF1 O Zero Input Detect 1 Pin 6 CAD0 I Chip Address 0 Pin 7 ACKSN I Auto Setting Mode Disable

15、Pin (Pull-down Pin) “L”: Auto Setting Mode, “H”: Manual Setting Mode 8 PDN I Power-Down Mode Pin When at “L”, the AK4358 is in the power-down mode and is held in reset. The AK4358 should always be reset upon power-up. 9 BICK I Audio Serial Data Clock Pin 10 MCLK I Master Clock Input Pin An external

16、TTL clock should be input on this pin. 11 DVDD - Digital Power Supply Pin, +4.75+5.25V 12 DVSS - Digital Ground Pin 13 SDTI4 I DAC4 Audio Serial Data Input Pin 14 SDTI1 I DAC1 Audio Serial Data Input Pin 15 SDTI2 I DAC2 Audio Serial Data Input Pin 16 SDTI3 I DAC3 Audio Serial Data Input Pin 17 LRCK

17、I L/R Clock Pin 18 I2C I Control Mode Select Pin “L”: 3-wire Serial, “H”: I2C Bus 19 CCLK/SCL I Control Data Clock Pin I2C = “L”: CCLK (3-wire Serial), I2C = “H”: SCL (I2C Bus) 20 CDTI/SDA I/O Control Data Input Pin I2C = “L”: CDTI (3-wire Serial), I2C = “H”: SDA (I2C Bus) 21 CSN/CAD1 I Chip Select

18、Pin I2C = “L”: CSN (3-wire Serial), I2C = “H”: CAD1 (I2C Bus) 22 DCLK I DSD Clock Pin 23 DSDL4 I DAC4 DSD Lch Data Input Pin 24 DSDR4 I DAC4 DSD Rch Data Input Pin 25 DSDL1 I DAC1 DSD Lch Data Input Pin 26 DSDR1 I DAC1 DSD Rch Data Input Pin 27 DSDL2 I DAC2DSD Lch Data Input Pin 28 DSDR2 I DAC2 DSD

19、Rch Data Input Pin 29 DSDL3 I DAC3 DSD Lch Data Input Pin 183 ASAHI KASEI AK4358 MS0203-J-01 2006/02 - 4 - PIN/FUNCTION No. Pin Name I/O Function 1 LOUT1- O DAC1 Lch Negative Analog Output Pin 2 LOUT1+ O DAC1 Lch Positive Analog Output Pin 3 DZF3 O Zero Input Detect 3 Pin 4 DZF2 O Zero Input Detect

20、2 Pin 5 DZF1 O Zero Input Detect 1 Pin 6 CAD0 I Chip Address 0 Pin 7 ACKSN I Auto Setting Mode Disable Pin (Pull-down Pin) “L”: Auto Setting Mode, “H”: Manual Setting Mode 8 PDN I Power-Down Mode Pin When at “L”, the AK4358 is in the power-down mode and is held in reset. The AK4358 should always be

21、reset upon power-up. 9 BICK I Audio Serial Data Clock Pin 10 MCLK I Master Clock Input Pin An external TTL clock should be input on this pin. 11 DVDD - Digital Power Supply Pin, +4.75+5.25V 12 DVSS - Digital Ground Pin 13 SDTI4 I DAC4 Audio Serial Data Input Pin 14 SDTI1 I DAC1 Audio Serial Data Inp

22、ut Pin 15 SDTI2 I DAC2 Audio Serial Data Input Pin 16 SDTI3 I DAC3 Audio Serial Data Input Pin 17 LRCK I L/R Clock Pin 18 I2C I Control Mode Select Pin “L”: 3-wire Serial, “H”: I2C Bus 19 CCLK/SCL I Control Data Clock Pin I2C = “L”: CCLK (3-wire Serial), I2C = “H”: SCL (I2C Bus) 20 CDTI/SDA I/O Cont

23、rol Data Input Pin I2C = “L”: CDTI (3-wire Serial), I2C = “H”: SDA (I2C Bus) 21 CSN/CAD1 I Chip Select Pin I2C = “L”: CSN (3-wire Serial), I2C = “H”: CAD1 (I2C Bus) 22 DCLK I DSD Clock Pin 23 DSDL4 I DAC4 DSD Lch Data Input Pin 24 DSDR4 I DAC4 DSD Rch Data Input Pin 25 DSDL1 I DAC1 DSD Lch Data Inpu

24、t Pin 26 DSDR1 I DAC1 DSD Rch Data Input Pin 27 DSDL2 I DAC2DSD Lch Data Input Pin 28 DSDR2 I DAC2 DSD Rch Data Input Pin 29 DSDL3 I DAC3 DSD Lch Data Input Pin 30 DSDR3 I DAC3 DSD Rch Data Input Pin 31 DIF0 I Audio Data Interface Format 0 Pin 32 ROUT4- O DAC4 Rch Negative Analog Output Pin 33 ROUT4

25、+ O DAC4 Rch Positive Analog Output Pin 34 VREFH I Positive Voltage Reference Input Pin 35 AVDD - Analog Power Supply Pin, +4.75+5.25V 36 AVSS - Analog Ground Pin 37 LOUT4- O DAC4 Lch Negative Analog Output Pin 38 LOUT4+ O DAC4 Lch Positive Analog Output Pin 39 ROUT3- O DAC3 Rch Negative Analog Outp

26、ut Pin 40 ROUT3+ O DAC3 Rch Positive Analog Output Pin 41 LOUT3- O DAC3 Lch Negative Analog Output Pin 42 LOUT3+ O DAC3 Lch Positive Analog Output Pin 43 ROUT2- O DAC2 Rch Negative Analog Output Pin 44 ROUT2+ O DAC2 Rch Positive Analog Output Pin H27U1G8F2BTR-BC(HDMI:IC391) ASAHI KASEI AK4358 MS0203

27、-J-01 2006/02 - 5 - 45 LOUT2- O DAC2 Lch Negative Analog Output Pin 46 LOUT2+ O DAC2 Lch Positive Analog Output Pin 47 ROUT1- O DAC1 Rch Negative Analog Output Pin 48 ROUT1+ O DAC1 Rch Positive Analog Output Pin Note: All input pins except pull-down pin should not be left floating. Rev 1.1 / Sep. 20

28、095 1 H27U1G8F2B Series 1 Gbit (128 M x 8 bit) NAND Flash VCC VSS WP CLE ALE RE WE CEIO0IO7 R/B NC NC NC NCNC NCNC NC CLE ALEVss Vss Vss Vcc Vcc NC NC NC WP RE CE WERB NC NC NC NC NC NC NC NC NC NC NC NC NC I/O0 I/O1 I/O9 I/O2 I/O3 I/O10 I/O11I/O4 I/O15 I/O12I/O14 I/O13 I/O6 I/O7 I/O5 NC NCNCNC NC P

29、RE I/O8 NC NCNC NCNC A B C D E F G H J K L M 1 2 3 4 5 6 7 8 9 10 ? ? ? Figure 2 : 48-TSOP1 / 63-FBGA Contact, x8 Device IO7 - IO0Data Input / Outputs CLECommand latch enable ALEAddress latch enable CEChip Enable RERead Enable WEWrite Enable WPWrite Protect R/BReady / Busy VccPower Supply VssGround

30、NCNo Connection Figure 1 : Logic Diagram Table 1 : Signal Names ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 184 H27U1G8F2BTR-BCPinFunction H27U1G8F2BTR-BCBlockDiagram Rev 1.1 / Sep. 20096 1 H27U1G8F2B Series 1 Gbit (128 M x 8 bi

31、t) NAND Flash 1.2 PIN DESCRIPTION Table 2 : Pin Description NOTE : 1. A 0.1uF capacitor should be connected between the Vcc Supply Voltage pin and the Vss Ground pin to decouple the current surges from the power supply. The PCB track widths must be sufficient to carry the currents required during pr

32、ogram and erase operations. Pin NameDescription IO0 IO7 DATA INPUTS/OUTPUTS The IO pins allow to input command, address and data and to output data during read / program operations. The inputs are latched on the rising edge of Write Enable (WE). The I/O buffer float to High-Z when the device is dese

33、lected or the outputs are disabled. CLE COMMAND LATCH ENABLE This input activates the latching of the IO inputs inside the Command Register on the Rising edge of Write Enable (WE). ALE ADDRESS LATCH ENABLE This input activates the latching of the IO inputs inside the Address Register on the Rising e

34、dge of Write Enable (WE). CE CHIP ENABLE This input controls the selection of the device. WE WRITE ENABLE This input acts as clock to latch Command, Address and Data. The IO inputs are latched on the rise edge of WE. RE READ ENABLE The RE input is the serial data-out control, and when active drives

35、the data onto the I/O bus. Data is valid tREA after the falling edge of RE which also increments the internal column address counter by one. WP WRITE PROTECT The WP pin, when Low, provides an Hardware protection against undesired modify (program / erase) operations. R/B READY BUSY The Ready/Busy out

36、put is an Open Drain pin that signals the state of the memory. Vcc SUPPLY VOLTAGE The Vcc supplies the power for all the operations (Read, Write, Erase). VssGROUND NCNO CONNECTION Rev 1.1 / Sep. 200915 1 H27U1G8F2B Series 1 Gbit (128 M x 8 bit) NAND Flash Figure 4 : Block Diagram ADDRESS REGISTER/ C

37、OUNTER PROGRAM ERASE CONTROLLER HV GENERATION COMMAND INTERFACE LOGIC COMMAND REGISTER DATA REGISTER IO RE BUFFERS Y DECODER PAGE BUFFER X D E C O D E R 1024 Mbit + 32 Mbit NAND Flash MEMORY ARRAY WP CE WE CLE ALE A27 A0 185 W9825G6JH-6(HDMI:IC392) W9825G6JH-6PinFunction 186 LAN8700(HDMI:IC322) LAN8

38、700BlockDiagram nINT/TX_ER/TXD4 MDC CRS/PHYAD4 MDIO nRST TX_EN VDD_CORE VDD33 LINK/PHYAD1 ACTIVITY/PHYAD2 FDUPLEX/PHYAD3 XTAL2 CLKIN/XTAL1 RXD3/nINTSEL RXD1/MODE1 RXD2/MODE2 TXD3 RX_CLK/REGOFF TX_CLK RX_ER/RXD4 VDDIO TXD1 TXD0 TXD2 COL/RMII/CRS_DV TXP RXN VDDA3.3 EXRES1 VDDA3.3 RXP VDDA3.3 USB3300 H

39、i-Speed USB2 ULPI PHY 32 Pin QFN 1 2 3 4 5 6 7 8 LAN8700/LAN8700I MII/RMII Ethernet PHY 36 Pin QFN GND FLAG 10 11 12 13 14 15 16 24 23 22 21 20 19 32 31 30 29 28 SPEED100/PHYAD0VD_XR9 RXD0/MODE0 17 TXN18 27 26 25 36 35 34 33 10M Rx Logic 100M Rx Logic DSP System: Clock Data Recovery Equalizer Analog

40、-to- Digital 100M PLL Squelch SAA7121 PINNING SYMBOLPINI/ODESCRIPTION res.1reserved SP2Itest pin; connected to digital ground for normal operation AP3Itest pin; connected to digital ground for normal operation LLC4Iline-locked clock; this is the 27 MHz master clock for the encoder VSSD15Idigital gro

41、und 1 VDDD16Idigital supply voltage 1 RCV17I/Oraster control 1 for video port; this pin receives/provides a VS/FS/FSEQ signal RCV28I/Oraster control 2 for video port; this pin provides an HS pulse of programmable length or receives an HS pulse MP79I MPEG port; it is an input for“CCIR 656” style mult

42、iplexed Cb Y, Cr data MP610I MP511I MP412I MP313I MP214I MP115I MP016I VDDD217Idigital supply voltage 2 VSSD218Idigital ground 2 RTCI19IReal Time Control input; if the LLC clock is provided by an SAA7111 or SAA7151B, RTCI should be connected to pin RTCO of the decoder to improve the signal quality r

43、es.20reserved SA21Ithe I2C-bus slave address select input pin; LOW: slave address = 88H, HIGH = 8CH res.22reserved res.23reserved C24Oanalog output of the chrominance signal VDDA125Ianalog supply voltage 1 for the C DAC res.26reserved Y27Oanalog output of VBS signal VDDA228Ianalog supply voltage 2 f

44、or the Y DAC res.29reserved CVBS30Oanalog output of the CVBS signal VDDA331Ianalog supply voltage 3 for the CVBS DAC VSSA132Ianalog ground 1 for the DACs VSSA233Ianalog ground 2 for the oscillator and reference voltage XTALO34Ocrystal oscillator output (to crystal) XTALI35Icrystal oscillator input (

45、from crystal); if the oscillator is not used, this pin should be connected to ground VDDA436Ianalog supply voltage 4 for the oscillator and reference voltage XCLK37Oclock output of the crystal oscillator 190 R2A15220FP(AUDIO:IC471) 8-CHANNEL ELECTRONIC VOLUME With 14-Input selector And Tone control

46、R2A15220FPR2A15220FP PRELIMINARY Notice ; This is not a final specification. Some parametric limits are subject to change. 2 / 18 CONFIDENTIAL R2A15220FP-87D BLOCK DIAGRAM AND PIN CONFIGURATION (TOP VIEW) AGND SWC SLC INLB/RECL2 INRB/RECR2 INR11/RECR5 INL10/RECL4 RECR3 INL11/RECL5 FLIN1 RECL3 CIN1 F

47、RIN1 SLIN1 SWIN1 AVEE MUTE FLIN2 FRIN2 SLIN2 SRIN2 CIN2 SWIN2 SBLIN2 SBRIN2 AVCC TREL BASSL1 BASSL2 FLOUT FLC FROUT AGND FRC ADCR SBLIN1 SRIN1 SBRIN1 SBL OUT ADCL SBR OUT SLOUT SBRC SROUT SWOUT SRC COUTINL5 INL1 INR1 INL2 INR2 INL3 INR3 INL4 INR4 INR5 INL6 INR6 INL7 INR7 INL8 INR8 INLA/RECL1 INRA/RE

48、CR1 INL9 INR9 SUBR1 SUBL1 INR10/RECR4 DATA CLOCK BASSR1 BASSR2 AGND AGND SBRCIN SBLCIN AGND SBLC FR Pre-OUT FL Pre-OUT SBR Pre-OUT TRER SUBR2 SUBL2 SRCIN SLCIN SR Pre-OUT SL Pre-OUT SBL Pre-OUT INR12 INL12 INR13 INL13 INR14 INL14 CC AGND DGND REC ATT 0/-6/-12/-18dB Bass/ Treble -14+14dB (2dB step) +42-95dB, -(0.5dBstep) +42-95dB, -(0.5dBstep)