Onkyo-TXSR705-avr-sm 电路图 维修手册.pdf

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1、TX-SR705/SA705 SERVICE MANUAL Ref. No. 3997 072007 AV RECEIVER MODEL TX-SR705 MODEL TX-SA705 TX-SR705 Black, Golden and Silver models 220-240V AC, 50Hz 220-240V AC, 50/60Hz 220-240V AC, 50/60Hz B MMP, MMA, S MMP, MMA B MMO, S MMO G MMQ, MMK, MMT TX-SA705 Golden models 220-240V AC, 50/60HzG MMR RC-69

2、3M SAFETY-RELATED COMPONENT WARNING! COMPONENTS IDENTIFIED BY MARK ON THE SCHEMATIC DIAGRAM AND IN THE PARTS LIST ARE CRITICAL FOR RISK OF FIRE AND ELECTRIC SHOCK. REPLACE THESE COMPONENTS WITH ONKYO PARTS WHOSE PART NUMBERS APPEAR AS SHOWN IN THIS MANUAL. MAKE LEAKAGE-CURRENT OR RESISTANCE MEASUREM

3、ENTS TO DETERMINE THAT EXPOSED PARTS ARE ACCEPTABLY INSULATED FROM THE SUPPLY CIRCUIT BEFORE RETURNING THE APPLIANCE TO THE CUSTOMER. B MDC, S MDC, G MDT120V AC, 60Hz RadioFans.CN 收音机爱 好者资料库 EXPLODED VIEWS-1 TX-SR705/SA705 TX-SR705/SA705 A004 x 5 pcs. A003 x 8 pcs. A061 A304 x 6 pcs. A004 x 7 pcs. A

4、004 x 2 pcs. A004 x 2 pcs. A004 x 2 pcs. A004 x 4 pcs. A004 x 3 pcs. A004 x 2 pcs. A004 x 2 pcs. A004 x 2 pcs. A004 x 2 pcs. A015 x 3 pcs. A002 A006 U06 U07 A306 A010 A063 A065A008 A005 A007 A009 A301 A303 P701 A302 U13 U16 U10 A016 x 2 pcs. A025 x 4 pcs. A306 x 4 pcs. A308 x 4 pcs. A309 x 4 pcs. A3

5、11 x 4 pcs. A023 x 2 pcs. A015 x 47 pcs. A037 x 4 pcs. P6607A x 4 pcs. P6602A x 6 pcs. P6601A x 8 pcs. F6901 F903 F901 F910 F910 F6902 P901 ( DC Type) ( All Type Except DC) A013 A020 U01 U22 U05 U23 U12 U20 U011 U17 U24 U18 U02 U08 U09 U04 U11 U03 U14 U15 A022 A001 A075 A075 A073 A075 A308 A305 A313

6、 A004 P692 P691 A004 A004 A004 A024 A024 A024 A074 A024 A024 A024 A004 A027 A016 A016 A016 A045 A047 A047 A042 A049 A051 P4008 P101 A039 A021 A041 T901 Refer to in EXPLODED VIEWS-2 RadioFans.CN 收音机爱 好者资料库 EXPLODED VIEWS-2 TX-SR705/SA705 TX-SR705/SA705 Q6056 Q6066 Q6055 Q6065 Q6054 Q6064 Q6053 Q6063

7、Q6052 Q6062 Q6051 Q6061 Q6050 Q6060 Q6050A x 2 pcs. Q6050B x 6 pcs. A059 x 14 pcs. RadioFans.CN 收音机爱 好者资料库 TX-SR705/SA705 BLOCK DIAGRAMS-1 AUDIO SECTION TX-SR705/SA705 A 1 2 3 4 5 BCDEFGH MAIN L MAIN R SUB R SUB L MAIN R REC L REC R MAIN L SUB R SUB L 38 39 37 36 SPRLB (PWRED Z2) SPRLF (H/P) FRL CSR

8、L SBRL Z2RL Z2MUTE SBMUTE AMUTE I2S(DVD Audio) I2S(DIR/ADC) SETUP MIC L R L R L R L R L R L R L R L R L R L R L R L R L R PHONO TAPE IN TAPE OUT CD TUNER (FRONT IN) AUX INPUT VCR/DVR IN VCR/DVR OUT CBL/SAT IN DVD C/SW FRONT SURROUND C SW GAME/TV IN SURROUND BACK TX OUT HDMI MIC AMP SPEAKER TERMINALS

9、 (TX-SA705 Only) SDRAM 16M Bit FLASH ROMSDRAM 16M bit FLASH ROMSDRAM 16M bit FLASH ROM TMS320DA790 or TMS320DA710 DSP1DSP2 DSP3 FRONT LEFT FRONT RIGHT CENTER SURR. LEFT SURR. RIGHT SUUR. BACK LEFT SUUR. BACK RIGHT LEFT ZONE 2 SPEAKERS RIGHT HEADPHONES +29dB +29dB +29dB +29dB +29dB +29dB +29dB SW C S

10、BL SBR SL SR FL FR TONE TONE SW FL FR C SL SBR SR SBL FL SUB L Q5501 R2S15211FPAudio Processor (Switch, Tone CDIN is the input data line for control port interface in SPI mode. 2 3 4 51 5 52 6 7 8 9 22 AD0/CS10Address Bit 0 (I C)/Control Port Chip Select (SPI) (Input) - AD0 is a chip address pin in

11、I C mode; CS is the chip select signal in SPI mode. INT11Interrupt (Output) - The CS42528 will generate an interrupt condition as per the Interrupt Mask register. RST12Reset (Input) - The device enters a low power mode and all internal registers are reset to their default settings when low. AINR- AI

12、NR+ 13 14 Differential right Channel Analog Input (Input) - Signals are presented differentially to the delta-sigma modulators via the AINR+/- pins. AINL- AINL+ 15 16 Differential right Channel Analog Input (Input) - Signals are presented differentially to the delta-sigma modulators via the AINR+/-

13、pins. VQ17Quiescent Voltage (Output) - Filter connection for internal quiescent reference voltage. FILT+18Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits. REFGND19Reference Ground (Input) - Ground reference for the internal sampling circuits. AOUTA

14、1 +, - AOUTB1 +, - AOUTA2 +, - AOUTB2 +, - AOUTA3 +, - AOUTB3 +, - AOUTA4 +, - AOUTB4 +, - 36, 37 35, 34 32, 33 31, 30 28, 29 27, 26 22, 23 21, 20 Differential Analog Output (Output) - The full-scale differential analog output level is specified in the Analog Characteristics specification table. 2 2

15、 VA VARX 24 41 Analog Power (Input) - Positive power supply for the analog section. AGND 25 40 Analog Ground (Input) - Ground reference. Connectes to analog ground. TX-SR705/SA705 IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS -6 Q1101: CS42528(8 ch CODEC with S/PDIF Receiver) TERMINAL DESCRIPTION (2/2

16、) Pin Name#Pin Description VA VARX 24 41 Analog Power (Input) - Positive power supply for the analog section. AGND25 40 Analog Ground (Input) - Ground reference. Connects to analog ground. MUTEC38Mute Control (Output) - The Mute Control pin outputs high impedance following an initial power -on con-

17、dition or whenever the PDN bit is set to a 1, forcing the codec into power -down mode. The signal will remain in a high impedance state as long as the part is in power-down mode. The Mute Control pin goes to the selected active state during reset, muting, or if the master clock to left/right clock f

18、requency ratio is incorrect. This pin is intended to be used as a control for external mute circuits to prevent the clicks and pops that can occur in any single supply system. The use of external mute circuits are not manda- toy but may be desired for designs requiring the absolute minimum in extran

19、eous clicks and pops. LPFLT39PLL Loop Filer (Output) - An RC network should be connected between this pin and ground. RXP7/GPO7 RXP6/GPO6 RXP5/GPO5 RXP4/GPO4 RXP3/GPO3 RXP2/GPO2 RXP1/GPO1 42 43 44 45 46 47 48 S/PDIF Receiver Input/ General Purpose Output (Input/ Output) - Receiver inputs for S/PDIF

20、encoded data. The CS42528 has an internal 8:2 multiplexer to select the active receiver port, according to the Receiver Mode Control 2 resister. These pins can also be configured as general purpose output pins, ADC Overflow indicators or Mute Control outputs according to the RXP/General Purpose Pin

21、Control resisters. RXP049S/PDIF Receiver Input (Input) - Dedicated receiver input for S/PDIF encoded data. TXP50S/PDIF Transmitter Output (Output) - S/PDIF encoded data output, mapped directly from one of the receiver inputs as indicated by the Receiver Mode Control 2 resister. VLP53Serial Port Inte

22、rface Power (Input) - Determines the required signal level for the serial port interfaces. SAI_SDOUT54Serial Audio Interface Serial Data Output (Output) - Output for twos complement serial audio PCM data from the S/PDIF incoming stream. This pin can also be configured to transmit the output of the i

23、nter- nal and external ADCs. RMCK55Recovered Master Clock (Output) - Recovered master clock output from the External Clock Reference CX_SDOUT56CODEC Serial Data Output (Output) - Output for twos complement serial audio data the internal and external ADCs. ADCIN1 ADCIN2 58 57 External ADC Serial Inpu

24、t (Input) - The CS42528 provides for up two external stereo analog to digital converter inputs to provide a maximum of six channels on serial data output line when the CS42528 is placed in One Line mode. OMCK59External Reference Clock (Input) - External clock reference that must be within the ranges

25、 specified in currently active on the serial audio data line. SAI_LRCK60Serial Audio Interface Left/Right Clock (Input/Output) - Determines which channel, Left of Right, is currently active on the serial audio data line. SAI_SCLK61Serial Audio Interface Serial Clock (Input/Output) - Serial clock for

26、 the Serial Audio Interface IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS -7 Q1201: CS4398-CZZ(Multi-bit DAC with Volume Control) TX-SR705/SA705 BLOCK DIAGRAM PIN CONFIGURATION IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS -8 Q1201: CS4398-CZZ(Multi-bit DAC with Volume Control) TX-SR705/SA705 TERMINAL D

27、ESCRIPTION IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS -9 Q1601: NJU7312AM(Analog Function Switch) TX-SR705/SA705 L1 L2 L3 L-COM1 L4 L5 L6 L-COM2 L7 L8 L-COM3 ST R1 R3 R2 R-COM1 R4 R5 R6 R-COM2 R7 R8 R-COM3 CK DATA VSS VDD VEE Pin No.Pin NameDescription 1 2 3 4 5 6 7 8 9 10 11 12 14 15 16 17 19 20 2

28、1 22 23 24 25 26 27 28 29 30 Pin No.Pin NameDescription VEE L1 L2 L3 L4 L-COM1 L5 L6 L-COM2 L7 L8 L-COM3 ST VSS CK DATA R-COM3 R8 R7 R-COM2 R6 R5 R-COM1 R4 R3 R2 R1 VDD Negative Voltage Supply Analog switch input/output Analog switch input/output Analog switch input/output Analog switch input/output

29、 L1, L2, L3 Common Analog switch input/output Analog switch input/output L4, L5, L6 common Analog switch input/output Analog switch input/output L7, L8 Common Chip enable GND Clock input/output Data input R7, R8 Common Analog switch input/output Analog switch input/output R4, R5, R6 Common Analog sw

30、itch input/output Analog switch input/output R1, R2, R3 Common Analog switch input/output Analog switch input/output Analog switch input/output Analog switch input/output Positive voltage supply Control Circuit Latch Circuit Level Shifter Latch Circuit Level Shifter BLOCK DIAGRAM TERMINAL DESCRIPTIO

31、N IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS -10 Q3401: D790E001BZDH275/D710E001BZDH275 (Audio DSP) TX-SR705/SA705 BLOCK DIAGRAM System Diagram Device Block Diagram Program/Data RAM 256K Bytes 256 256 Program/Data ROM Page1 256K Bytes 256 256 256K Bytes ROM Page3 Program/Data Program/Data ROM Page2

32、 256K Bytes 3232 DMPPMP CSP32 256 Program Cache 32K Bytes 64 D1 Data R/W R/W Data D2 64 256 Program FetchINTI/O C67x+ CPU Memory Controller 32 High-Performance Crossbar Switch 32 McASP DMA Bus JTAG EMU 32 32 32 32 32 32 32 32 Peripheral Configuration Bus EMIF 32 Events In 32 MAX1MAX0 32 CONTROL 32 I

33、nterrupts Out I/O dMAX McASP0 16 Serializers McASP1 6 Serializers McASP2 2 Serializers + DIT SPI1 SPI0 I2C1 I2C0 RTI32 UHPI PLL Peripheral Interrupt and DMA Events 32 32 32 32 32 256K Bytes RAM Bytes ROM 768K Memory Controller C67x+ DSP Core Program Cache Crossbar Switch EMIFUHPIdMAX McASP0 SPI1 McA

34、SP1 I2C0 I2C1 RTI SPIO McASP2 PLLOSC ASYNC FLASH 100-MHz/ 133-MHz SDRAM DSP Host Microprocessor Audio Zone 1 SPI or I2C Control (optional) Audio Zone 2 Audio Zone 3 CODEC, DIR, ADC, DAC, DSD, Network Network ADC, DAC, DSD, CODEC, DIR, TDM Port Digital Out, High Speed Parallel Data DSP Control SPI or

35、 I2C 6 Independent Audio Zones (3 TX + 3 RX) 16 Serial Data Pins PIN CONFIGURATION(1/2) IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS -11 TX-SR705/SA705 Q3401: D790E001BZDH275/D710E001BZDH275 (Audio DSP) PIN MAP PIN CONFIGURATION(2/2) IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS -12 TX-SR705/SA705 Q340

36、1: D790E001BZDH275/D710E001BZDH275 (Audio DSP) Bottom View 13 24 5 68 79 10 11 14 15 12 13 16 N A C B D F E L G H J K M P T R TERMINAL DESCRIPTION(1/5) BALL SIGNAL NAMETYPE(1)PULL(2)GPIO(3)DESCRIPTION NO. Clocks OSCINJ2I-N1.2-V Oscillator Input OSCOUTJ3O-N1.2-V Oscillator Output OSCVDDJ4PWR-NOscilla

37、tor 1.2-V VDDtap point (for filter only) OSCVSSJ1PWR-NOscillator VSStap point (for filter only) CLKINH2I-NAlternate clock input (3.3-V LVCMOS Input) PLLHVK2PWR-NPLL 3.3-V Supply Input (requires external filter) Device Reset RESETG2I-NDevice reset pin Emulation/JTAG Port TCKP1IIPUNTest Clock TMSK3IIP

38、UNTest Mode Select TDIL1IIPUNTest Data In TDOM2OZIPUNTest Data Out TRSTK4IIPDNTest Reset EMU0M1IOIPUNEmulation Pin 0 EMU1N1IOIPUNEmulation Pin 1 Power Pins Core Supply (CVDD)E6, E7, E8, E9, E10, E11, G5, G12, H5, H12, J5, J12, K5, K12, M6, M7, M8, M9, M10, M11 IO Supply (DVDD)A2, A15, B1, B16, D4, D

39、5, D12, D13, E4, E13, J14, M4, M13, N5, N12, P8, R1, R16, T2, T15 A1, A7, A10, A16, E5, E12, F5, F6, F7, F8, F9, F10, F11, F12, G1, G6, G7, G8, G9, G10, G11, G16, H3, Ground (VSS)H6, H7, H8, H9, H10, H11, J6, J7, J8, J9, J10, J11, K1, K6, K7, K8, K9, K10, K11, K16, L5, L6, L7, L8, L9, L10, L11, L12,

40、 M5, M12, T1, T7, T10, T16 A TERMINAL DESCRIPTION(2/5) IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS -13 TX-SR705/SA705 Q3401: D790E001BZDH275/D710E001BZDH275 (Audio DSP) BALL SIGNAL NAMETYPE(1)PULL(2)GPIO(3)DESCRIPTION NO. External Memory Interface (EMIF) Address and Control EM_A0J16O-N EM_A1J15O-N E

41、M_A2K15O-N EM_A3L16O-N EM_A4L15O-N EM_A5M16O-N EM_A6M15O-NEMIF Address Bus EM_A7N16O-N EM_A8N15O-N EM_A9P16O-N EM_A10H15O-N EM_A11P15O-N EM_A12P12OIPDN EM_BA0G15O-N SDRAM Bank Address and Asynchronous Memory Low-Order Address EM_BA1H16O-N EM_CS0F15O-NSDRAM Chip Select EM_CS2E15O-NAsynchronous Memory

42、 Chip Select EM_CASR3O-NSDRAM Column Address Strobe EM_RASF16O-NSDRAM Row Address Strobe EM_WET3O-NSDRAM Write Enable EM_CKET14O-NSDRAM Clock Enable EM_CLKR14O-NSDRAM Clock EM_WE_DQM0R4O-NWrite Enable or Byte Enable for EM_D7:0 EM_WE_DQM1T13O-NWrite Enable or Byte Enable for EM_D15:8 EM_WE_DQM2P13OI

43、PUNWrite Enable or Byte Enable for EM_D23:16 EM_WE_DQM3R15OIPUNWrite Enable or Byte Enable for EM_D31:24 EM_OED15O-NSDRAM Output Enable EM_RWE16O-NAsynchronous Memory Read/not Write Asynchronous Wait Input (Programmable Polarity) or EM_WAITD14IIPUN Interrupt (NAND) (1)TYPE column refers to pin direc

44、tion in functional mode. If a pin has more than one function with different directions, the functions are separated with a slash (/). (2)PULL column: IPD = Internal Pulldown resistor IPU = Internal Pullup resistor (3)If the GPIO column is Y, then in GPIO mode, the pin is configurable as an IO unless

45、 otherwise marked. A TERMINAL DESCRIPTION(3/5) IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS -14 TX-SR705/SA705 Q3401: D790E001BZDH275/D710E001BZDH275 (Audio DSP) BALL SIGNAL NAMETYPE(1)PULL(2)GPIO(3)DESCRIPTION NO. External Memory Interface (EMIF) Data Bus / Universal Host-Port Interface (UHPI) Addre

46、ss Bus Option EM_D0T8IO-N EM_D1R8IO-N EM_D2R7IO-N EM_D3T6IO-N EM_D4R6IO-N EM_D5T5IO-N EM_D6R5IO-N EM_D7T4IO-N EMIF Data Bus Lower 16 Bits EM_D8R13IO-N EM_D9T12IO-N EM_D10R12IO-N EM_D11T11IO-N EM_D12R11IO-N EM_D13R10IO-N EM_D14T9IO-N EM_D15R9IO-N EM_D16/UHPI_HA0N7IO/IIPDN EM_D17/UHPI_HA1P6IO/IIPDN EM

47、_D18/UHPI_HA2N6IO/IIPDN EM_D19/UHPI_HA3P5IO/IIPDN EM_D20/UHPI_HA4P4IO/IIPDN EM_D21/UHPI_HA5P3IO/IIPDN EM_D22/UHPI_HA6N4IO/IIPDN EM_D23/UHPI_HA7R2IO/IIPDN EMIF Data Bus Upper 16 Bits (IO) or UHPI Address Input (I) EM_D24/UHPI_HA8P11IO/IIPDN EM_D25/UHPI_HA9N11IO/IIPDN EM_D26/UHPI_HA10P10IO/IIPDN EM_D2

48、7/UHPI_HA11N10IO/IIPDN EM_D28/UHPI_HA12P9IO/IIPDN EM_D29/UHPI_HA13N9IO/IIPDN EM_D30/UHPI_HA14N8IO/IIPDN EM_D31/UHPI_HA15P7IO/IIPDN A TERMINAL DESCRIPTION(4/5) IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS -15 TX-SR705/SA705 Q3401: D790E001BZDH275/D710E001BZDH275 (Audio DSP) BALL SIGNAL NAMETYPE(1)PULL

49、(2)GPIO(3)DESCRIPTION NO. Universal Host-Port Interface (UHPI) Data and Control UHPI_HD0K13IOIPDY UHPI_HD1K14IOIPDY UHPI_HD2M14IOIPDY UHPI_HD3L13IOIPDY UHPI_HD4L14IOIPDY UHPI_HD5N13IOIPDY UHPI_HD6N14IOIPDY UHPI_HD7P14IOIPDY UHPI Data Bus Lower 16 Bits UHPI_HD8E14IOIPDY UHPI_HD9F14IOIPDY UHPI_HD10F13IOIPDY UHPI_HD11G14IOIPDY UHPI_HD12G13IOIPDY UHPI_HD13H14IOIPDY UHPI_HD14H13IOIPDY UHPI_HD15J13IOIPDY UHPI_HD16/HHWILH1IO/IIPDY UHPI_HD17G3IOIPDY UHPI_HD18G4IOIPDY UHPI_HD19F3IOIPDY UHPI_HD20F4IOIPDY UHPI Data Bus Upper 16 Bits (IO) in the following modes: UHPI_HD21E3IOIPDY