Arcam-Alpha8-cd-sm 电路图 维修手册.pdf
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1、ALPHA 7/8/9 CD SERVICE MANUALALPHA 7/8/9 CD SERVICE MANUAL Arcam Alpha 7/8/9 CD Service Manual Issue 1 Serial No. 0001 - (Paul Newton July 96) Circuit Description The following notes describe the operation of the Alpha 7/8/9 CD players. They include the circuitry on the main, DAC and display PCBs bu
2、t not that on the servo PCB attached to the mechanism. Power Supplies The mains input is fitted with inductors L2,3,6,7 to filter electromagnetic interference coming out of the player. Mains transformer T201 has three secondary windings supplying two separate power supplies and an AC supply for the
3、display filament: Analogue Supply Bridge rectifier D4,5,6,7 and reservoir capacitors C209-C212 produce unregulated split rails of about +/-22V. Z204 and Z205 provide regulated outputs of +18V and -18V respectively that power the opamps in the audio output stage. Since there is no power switch on thi
4、s secondary, the analogue supplies are always connected. Digital Supply Switch SW201-A disconnects the digital secondary winding when the Power switch is out. An unregulated supply of about 11V is produced by the bridge rectifier D8,9,10,11 and reservoir capacitor C36. This is then regulated to prov
5、ide three +5 volt supplies (Z208 general logic supply, Z207 DAC supply, Z203 system clock generator supply) and a +7.3v supply for themechanism and motor drive circuits(Z206). A -30v supply is formed by Z209 and associated components to power the display grid. Muting When the unit is turned off SW20
6、1-A discharges capacitor C29 quickly. This along with the AMUTE signal from the microprocessor, controls the output mute transistors Q1,101 via level shifter Q3. Clock Generator The system clock is generated by a discrete oscillator based around Q2 and 16.9344MHz oscillator X1. The output of Q2 is a
7、mplified and buffered by inverters Z202-E & D and sent to the clock input of the DAC Z201. DAC & Audio Outputs (Alpha 7 only) The DAC is a Delta-Sigma design from Burr Brown, the PCM1710U. The serial digital data from the decoder Z206 is input to pins 1 to 3. The system clock is input to pin 5. The
8、DAC is powered entirely from one 5V supply, although it is split and decoupled between the analogue and digital sections of the device. The analogue outputs from each channel are processed identically.Three poles of filtering are provided by the active filter based around Z1-A. Z1-B buffers the audi
9、o output and sets the output level. Muting is provided by turning on Q1 and Q101. DAC & Audio Outputs (Alpha 8 only) This is a similar circuit as the one used on the Arcam Alpha 6 DAC PCB but designed for Sony format input data and a better digital filter, the SM5843AP1, Z14.The digital filter is us
10、ed with a SM5864AP 20-bit DAC chip, Z12, (described here as a PWM noise shaper to avoid confusion with the 1-bit DAC Latch which follows it). The output from this is re-latched by Z7, Z8. Digital FilterA PIC micro on the mother board controls the filter with the signals RB0 to RB7. The SM5843 filter
11、 has internal pull-up resistors on its inputs resulting in RB4 & RB5 being logic 1. The SM5843APT requires several control lines from the PIC. RB7 FSEL2, Selects sampling rate for de-emphasis. Static low for 44.1K. RB6 FSEL1, Selects sampling rate for de-emphasis. Static low for 44.1K. RB5 IW2N, Sel
12、ects input word length. Static high for 16 bits. RB4 MDT, Serial data input for volume control. Burst at switch-on for setting to full. RB3 RSTN, Reset line. Short pulse low at switch on, then static high. RB2 MLEN, Serial data latch input for volume control. RB1 MCK, Serial clock input for volume c
13、ontrol. RB0 Not connected. No Dither On Silence The digital filter adds dither to the output signal. This improves the low-level performance of the DAC. The PWM filter normally mutes when it detects digital silence to prevent any unwanted noise and idle-tones on the audio outputs when no music is pl
14、aying. A slight click is audible when this happens. Unfortunately, the added dither prevents this mute from operating because it holds it open. Q11 detects digital silence on the data input to the filter. When silence is detected, the dither function is switched off RadioFans.CN 收音机爱 好者资料库 ALPHA 7/8
15、/9 CD SERVICE MANUALALPHA 7/8/9 CD SERVICE MANUAL 16.9344MHz Low-Jitter System Clock, X1, Q5 & Z13 SM5843AP1 Digital Filter, Z14 74HC74 Latches, Z7 & Z8 SM5864 PWM Noise Shaper, Z12 Analogue Filter, Z1, Z2, Z3, Z4 Sony Format Digital Audio Control from PIC micro (Z211) on main pcb Audio out Clock Bl
16、ock Diagram of Alpha 8 DAC PCB allowing the PWM filters mute to operate as normal. Mute Relay The mute relay is controlled from the PIC micro via RA0 after switch-on. In Standby mode, XRST is low which interrupts the relay via Q9. RA0 is low when the CD player comes out of standby mode and goes high
17、 after a short settling delay. The power rail, RLYPWR, is un-regulated and has a small reservoir capacitor (on the mother board) so that the relay is released very soon after the mains is disconnected from the CD player before the other power supply rails collapse. PWM noise shaper To reduce EMC, th
18、e clock signal going into this chip, Z12, is very weak on the XTI pin (23) pin, taken directly off Q5. This is amplified so that there should be a larger signal on the CKO pin (26). The PWM output on pins 11, 13, 16 and 18 can be resolved into an audio waveform on a scope simply by measuring them th
19、rough a 100K resistor. The same is true for the PWM signals through the latch and the level shifter. Latch The PWM data from Z12 is re-latched using 74HC74 latches, Z7 and Z8.The power supply for these chips is the DAC voltage reference and the output drives the analogue filter stage directly. The l
20、atches reduce any edge-timing jitter induced on the PWM signal coming from Z12. Analogue filter The first half of the analogue filter, Z3 and Z4 is balanced. The signal through one side of the op-amp, pin 1, should be phase inverted with respect to the other, pin 7. These signals should be viewed on
21、 a scope through a 100K resistor since there may still be quite a lot of RF noise on the signal. Z1 and Z2 filter the audio signal further and also convert the balanced signal into a single ended signal. Z18 acts as a DC servo to reduce the output offset voltage. This has a very large time constant
22、so an offset as high as 50mV is possible when the unit is first plugged in. This reduces to less than 3mV after 10 minutes and stays low if the unit is switched off and on with the Standby button. RadioFans.CN 收音机爱 好者资料库 ALPHA 7/8/9 CD SERVICE MANUALALPHA 7/8/9 CD SERVICE MANUAL Test Points Marked o
23、n Circuit Diagram Only Test PointsMeasurement Information 17MHzClock Output to mother board. 16.9344MHz +/- 40ppm, 4V to 5V peak to peak square wave. AGNDAnalogue ground point. AMUTEDigital audio mute input on SK203. 0V=off, 5V=Mute. CKSerial Data clock input on SK203. Sony format. DASerial Data dat
24、a input on SK203. Sony format. CLKSYNCCrystal clock override. A 16.9344MHz HCMOS clock can be injected from an external source. DEEMDe-emphasis select input on SK203. 0V=off, 5V=On. DGNDDigital ground point. LOUTLeft channel audio output at SK1. Measure d.c. offset at switch-on and after 1 minute, s
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