Cambridge-DVD53-dvd-sm 电路图 维修手册.pdf
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1、OPEN CLOSE PREV NEXTPLAYPAUSESTOP POWER SERVICE MANUAL DVD53/55 RadioFans.CN 收音机爱 好者资料库 CONTENTS 1. SAFETY PRECAUTIONS1 2. PREVENTION OF ELECTRO STATIC DISCHARGE(ESD)TO ELECTROSTATICALLY SENSITIVE(ES)DEVICES1 4. PREVERTION OF STATIC ELECTRICITY DISCHARGE3 5. ASSEMBLING AND DISASSEMBLING THE MECHANIS
2、M UNIT4 5.1 OPTICAL PICKUP UNIT EXPLOSED VIEW AND PART LIST 4 5.2 BRACKET EXPLOSED VIEW AND PART LIST 6 6. ELECTRICAL CONFIRMATION8 6.1 VIDEO OUTPUT (LUMINANCE SIGNAL) CONFIRMATION8 6.2 VIDEO OUTPUT(CHROMINANCE SIGNAL) CONFIRMATION9 7. MPEG BOARD CHECK WAVEFORM10 8. IC BLOCK DIAGRAM 1, 2, 3 Clocks O
3、RDERING INFORMATION Part No.Clock FrequencyOrganizationInterfacePackage HY57V161610DTC-55I1 8 3 M H z 2Banks x 512Kbits x 16L V T T L 400mil 50pin TSOP II HY57V161610DTC-6I1 6 6 M H z HY57V161610DTC-7I1 4 3 M H z HY57V161610DTC-10I1 0 0 M H z 38 8.4 U203 SDRAM-HY57V1610D 2 Banks x 512k x 16 Bit Sync
4、hronous DRAM IC BLOCK DIAGRAM & DESCRIPTION PIN CONFIGURATION PIN DESCRIPTION PINP I N N A M ED E S C R I P T I O N C L KClock The system clock input. All other inputs are referenced to the SDRAM on the rising edge of CLK. C K EClock Enable Controls internal clock signal and when deactivated, the SD
5、RAM will be one of the states among power down, suspend or self refresh. C SChip SelectCommand input enable or mask except CLK, CKE and DQM B ABank AddressSelect either one of banks during both R A S and C A S activity. A0 A10Address Row Address : RA0 RA10, Column Address : CA0 CA7 Auto-precharge fl
6、ag : A10 R A S , C A S , W E Row Address Strobe, Column Address Strobe, Write Enable R A S , C A S and W E define the operation. Refer function truth table for details L D Q M , U D Q MData Input/Output MaskDQM control output buffer in read mode and mask input data in write mode D Q 0 D Q 1 5Data In
7、put/OutputMultiplexed data input / output pin VD D/VSSPower Supply/GroundPower supply for internal circuit and input buffer VD D Q/VS S QData Output Power/GroundPower supply for DQ N CNo ConnectionNo connection V S S D Q 1 5 D Q 1 4 V S S Q D Q 1 3 D Q 1 2 V D D Q D Q 1 1 D Q 1 0 V S S Q D Q 9 D Q 8
8、 V D D Q N C U D Q M C L K C K E N C A 9 A 8 A 7 A 6 V D D D Q 0 D Q 1 V S S Q D Q 2 D Q 3 V D D Q D Q 4 D Q 5 V S S Q D Q 6 D Q 7 V D D Q L D Q M W E C A S R A S C S A 1 1 A 1 0 A 0 A 1 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 5 0 4 9 4 8 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0
9、 3 9 3 8 3 7 3 6 3 5 3 4 3 3 3 2 3 1 3 0 2 9 5 0 p i n T S O P -I I 4 0 0 m i l x 8 2 5 m i l 0 . 8 m m p i n p i t c h A 2 A 3 V D D A 5 A 4 V S S 2 3 2 4 2 5 2 8 2 7 2 6 39 IC BLOCK DIAGRAM & DESRIPTION? FUNCTIONAL BLOCK DIAGRAM 1Mx16 Synchronous DRAM C o l u m n Addr. Latch & Counter Burst Length
10、 Counter Refresh Interval Timer Refresh Counter D Q 0 D Q 1 D Q 2 D Q 3 D Q 4 D Q 5 D Q 6 D Q 7 D Q 8 D Q 9 D Q 1 0 D Q 1 1 D Q 1 2 D Q 1 3 D Q 1 4 D Q 1 5 Address Register I/O ControlTest ModeMode Register Self Refresh Counter Column Decoder Sense AMP & I/O gates 512Kx16 Bank 0 Column Decoder Sense
11、 AMP & I/O gates 512Kx16 Bank 1 R A S C A S C S W E U D Q M L D Q M C K E Precharge Overflow Column Active Row Active Address0:10 C L K B A ( A 1 1 ) State Machine Row Decoder Row Addr. Latch/Predecoder Auto/Self Refresh Ref. Addr.0:11 Data Input/Output Buffers Row Addr. Latch/Predecoder 40 IC BLOCK
12、 DIAGRAM & DESRIPTION? ABSOLUTE MAXIMUM RATINGS Note : Operation at above absolute maximum rating can adversely affect device reliability. DC OPERATING CONDITION (TA= -40C to 85C ) Note : 1.All voltages are referenced to VS S = 0V. 2.VDD(min) is 3.15V when HY57V161610DTC-7I operates at C A S latency
13、=2 3.VIH(max) is acceptable 4.6V AC pulse width with 10ns of duration. 4.VIL(min) is acceptable -1.5V AC pulse width with 10ns of duration. AC OPERATING CONDITION (TA= - 40C to 85C , VD D=3.0V to 3.6V, VSS=0V) Note : 1. Output load to measure access times is equivalent to two TTL gates and one capac
14、itance(30pF). For details, refer to AC/DC output load circuit. 2. VDD(min) is 3.15V when HY57V161610DTC-7I operates at C A S latency=2 and tCK2=8.9ns ParameterS y m b o lRatingUnit Ambient TemperatureTA- 40 85C Storage TemperatureTS T G-55 125C Voltage on Any Pin relative to VSSVIN, VO U T-1.0 4.6V
15、Voltage on VD D relative to VSSVDD-1.0 4.6V Short Circuit Output CurrentIO S50m A Power DissipationPD1W Soldering TemperatureT i m eTS O L D E R26010C S e c ParameterSymbolMinT y p .M a xUnitNote Power Supply VoltageVDD, VDDQ3.03.33.6V1, 2 Input high voltageVIH2.03.0VDD + 0.3V1, 4 Input low voltageV
16、IL-0.500.8V1, 5 ParameterS y m b o lValueUnitNote AC input high / low level voltageVIH / VIL2.4/0.4V Input timing measurement reference level voltageVtrip1.4V Input rise / fall timetR / tF1n s Output timing measurement reference levelVoutref1.4V Output load capacitance for access time measurementC L
17、30pF1 IC BLOCK DIAGRAM & DESRIPTION? 41 SW1 1 SW2 2 SW3 3 SW4 4 DO 5 DIN 6 VSS 7 CLK 8 STB 9 KEY1 10 KEY2 11 KEY3 12 KEY4 13 VDD 14 S1 15 S2 16 S3 17 S4 18 S5 19 S6 20 S7 21 S8 22 S9 23 S10 24 S11 25 S12/G1 26 VEE 27 S13/G1 28 S14/G9 29 S15/G8 30 S16/G7 31 G6 32 G5 33 G4 34 G3 35 G2 36 G1 37 VDD 38
18、LED4 39 LED3 40 LED2 41 LED1 42 VSS 43 OSC 44 U401 UPD16312 C401 104 C403 101 C404 101 1 2 3 U403 HS0038A2 K408K404 K409 K407K403 K401 K402 D401 1N4148 D402 1N4148 D403 1N4148 -25V GRID5 GRID4 GRID3 GRID2 GRID1 VCC SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 VCC VFDST VFDCK VFDAT VCC KE
19、Y1 KEY2 KEY3 KEY4 GND SW4 SW3 SW2 MSW GND SEG12 SEG13 SEG14 SEG15 SEG16 VCC KEY4 KEY3 KEY2 KEY1 -25V FIL+ FIL- SEG1 SEG2 SEG3 VFDST VFDCK VFDAT IR GND GND C405 104 R415 100 IR VCC R405 33K R40133K R402 33K R403 33K R40433K R406 10K R407 10K R40810K R409 10K R410 10K R411 33K R412 33K R413 33K R414 3
20、3K GRID6 GRID5 GRID4 GRID3 GRID2 FIL- FIL+ K405 K406 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 R416 10K VCCC406 101 R417 10K VCC 2 3 4 1 5 XS402 XS05 2 3 4 1 5 XS401 XS05 C402 100uF/16V C407 100uF/16V R418 33R K410 F1 1 F1 2 P16 4 P13 7 P14 6 P15 5 P12 8
21、P11 9 P10 10 P9 11 P8 12 P7 13 P6 14 P5 15 P4 16 P3 17 P2 18 P1 19 NC 23 NC 24 NC 25 NC 26 5G 31 6G 32 1G 27 2G 28 3G 29 4G 30 F2 34 F2 35 NC 20 NC 21 NC 22 VFD401 VFD-35 GRID1 GRID6 9.SCHEMATIC & P.C.B WIRING DIAGRAM? FRONT SCHEMATIC DIAGRAM 42 FRONT SCHEMATIC DIAGRAM 43 U503 LM431A C515 104 L505 1
22、0uH/1A C506 223 L507 10uH/2A L506 10uH/2ABC502 275V 104 BC501 275V 104 L502 L501 RV501 07D471 F501 T1.6A/250V R K A ! ! ! R510 4.7K R509 10K R508 3.3K R506 330 R505 33ohm R502 120K/2W R503 39K/2W ! BCN502 SW-SPST ! ! U502 2501 TC502 47uF/50V TC501 47uF/400V D505 HER107 C502 103/1KV C503 101/1KV L503
23、 FB FL+ FL- -21V DGND +5V BC503 400V 221 L508 FB C505 101 C513 101 C509 101 C514 101 C511 101 +9V -9V DGND +3.3V C504 104 +5V DGND +9V OK AGND TC504 470uF/16V TC511 100uF/16V TC512 47uF/50V TC506 1000uF/10V TC505 1000uF/10V TC509 1000uF/10V TC510 1000uF/10V 2 3 4 1 5 CN501 XS05 D508 HER105 C507 101
24、TC503 470uF/16V R511 220R/1W FB 4 GND 1 D 2 VCC 3 U501 5L0380R R507 1K R504 1M R501 680K 2W ! 2 3 4 1 5 6 CN502 XS06 ! ! ! VOICE-DET SD+5V SA+5V +9V DGND DGND DGND 220V BCN501 IN 1 GND 2 OUT 3 U504 LM7805 TC508 100uF/16V TC507 470uF/10V SA+5V D510 HER303 ZD501 5.1V D506 HER105 D509 SR303 D511 HER105
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