marantz nr1506_u1b 维修电路原理图.pdf
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1、AV SURROUND RECEIVER NR1506 /U1B/N1B/N1SG/K1B NR1506 S1214V03DM/DG1603 Copyright 2016 D must connect recommended filter 44VCOMONoADC common voltage output; must connect external decoupling capacitor 45AGNDADGround, for ADC analog 46VCCADPower supply, 5.0 V (typ.), for ADC analog 47VINLINoADC analog
2、voltage input, left channel 48VINRINoADC analog voltage input, right channel (1) Schmitt trigger input (2) Schmitt trigger input (3) Open-drain configuration in I2C mode (4) Onboard pull-down resistor (50 k, typical) (5) CMOS Schmitt trigger input PCM9211 BLOCK DIAGRAM Clock/Data Recovery MPIO_A SEL
3、ECTOR MPIO_C SELECTOR MPIO _B SELECTOR ADC Com. Supply MPO0/1 SELECTOR MPO0 MPO1 MAIN OUTPUT SCKO BCK LRCK DOUT PORT RXIN8 RXIN9 RXIN10 RXIN11 DITOUT AUTO DIR ADC AUXIN0 AUXIN1 AUXIN2 AUTO DIR ADC AUXIN0 AUXIN1 AUXIN2 AUTO DIR ADC AUXIN0 AUXIN1 DIT Lock:DIR Unlock:ADC AUXIN2 AUXOUT OSC Divider XMCKO
4、 Divider XMCKO DITOUT RECOUT0 RECOUT1 AUXIN0 AUXIN1 ADC Standalone ADC Mode Control Function Control REGISTER POWER SUPPLY MC /SCL MDI/SDA MDO /ADR0 MS/ADR1 FILT PLL DIR Lock Detection ERROR/INT0 NPCM/INT1 ADC Clock (SCK/BCK/LRCK) (To MPIO _A & MPO0/1) ADC MODE DIR CS (48-bit) DIT CS (48-bit) DIR In
5、terrupt GPIO/GPO Data MPIO_A MPIO_B MPIO_C MPO0 MPO1 Divider (to MPIO_A) Secondary BCK/LRCK Selector RECOUT0 RECOUT1 SBCK/SLRCK DOUT RXIN7 SCKO/BCK/LRCK RXIN0 RXIN1 RXIN2 RXIN4/ASCKI0 RXIN3 RXIN5/ABCKI0 RXIN6/ALRCKI0 RXIN7/ADIN0RXIN7 RXIN6 RXIN5 RXIN4 RXIN3 RXIN2 RXIN1 RXIN0 MPIO_A0 MPIO_A1 MPIO_A2
6、MPIO_A3 VINL VINR VCOM MPIO _C0 MPIO _C1 MPIO _C2 MPIO _C3 XTI XTO AGNDVDDRXGNDRXDVDDVCCADAGNDADDGNDVCC ADC ANALOG DIR ANALOG ALL DIR ANALOG SPI/I C INTERFACE 2 Reset and Mode Set All Port f Calculator S DIR f Calculator S DIR P and P CD EXTRA DIR FUNCTIONS f Calculator S ERROR DETECTION Non-PCM DET
7、ECTION Flags DTS-CD/LD Detection Validity Flag User Data Channel Status Data BFRAME Detection Interrupt System MPIO_B3 MPIO_B2 MPIO_B1 MPIO_B0 RST PCM9211 SBAS495 JUNE 2010 BLOCK DIAGRAM Copyright 2010, Texas Instruments IncorporatedSubmit Documentation Feedback9 Product Folder Link(s): PCM9211 129
8、ADSP21487KSWZ-2B (HDMI : U1021) TOP VIEW (PINS DOWN) 1 44 45 89 88 132 176133 PIN 1 GND PAD (PIN 177) at BOTTOM Pin NamePin No.Pin NamePin No.Pin NamePin No.Pin NamePin No. SDDQM1VDD_EXT45DAI_P1089VDD_INT133 MS02DPI_P08 46VDD_INT90FLAG0134 SDCKE3DPI_P07 47VDD_EXT91FLAG1135 VDD_INT4VDD_INT48DAI_P2092
9、FLAG2136 CLK_CFG15DPI_P09 49VDD_INT93NC137 ADDR06DPI_P10 50DAI_P08 94FLAG3138 BOOT_CFG07DPI_P1151DAI_P14 95NC139 VDD_EXT8DPI_P12 52DAI_P04 96NC140 ADDR19DPI_P13 53DAI_P18 97VDD_EXT141 ADDR210DPI_P14 54DAI_P17 98NC142 ADDR311DAI_P0355 DAI_P16 99VDD_INT143 ADDR412NC56DAI_P12 100TRST144 ADDR513VDD_EXT5
10、7DAI_P15 101NC145 BOOT_CFG114NC58VDD_INT102EMU146 GND15NC59DAI_P11 103DATA0147 ADDR616NC60VDD_EXT104DATA1148 ADDR717NC61VDD_INT105DATA2149 NC18 VDD_INT62BOOT_CFG2106 DATA3150 NC19NC63VDD_INT107TDO151 ADDR820NC64AMI_ACK108DATA4152 ADDR921VDD_INT65GND 109VDD_EXT153 CLK_CFG022NC66THD_M110DATA5154 VDD_I
11、NT23NC67THD_P111DATA6155 CLKIN24VDD_INT68VDD_THD112VDD_INT156 XTAL25NC69 VDD_INT113DATA7157 ADDR1026WDTRSTO70VDD_INT114TDI158 SDA1027NC71MS1115SDCLK159 VDD_EXT28VDD_EXT72VDD_INT116VDD_EXT160 VDD_INT29DAI_P07 73WDT_CLKO117DATA8161 ADDR1130DAI_P13 74WDT_CLKIN118DATA9162 ADDR1231DAI_P19 75VDD_EXT119DAT
12、A10163 ADDR1732DAI_P0176 ADDR23120TCK164 ADDR1333DAI_P02 77ADDR22121DATA11165 VDD_INT34VDD_INT78ADDR21122DATA12166 ADDR1835NC79VDD_INT123DATA14167 RESETOUT/RUNRSTIN36NC80ADDR20124DATA13168 VDD_INT37NC81ADDR19125VDD_INT169 DPI_P01 38NC82VDD_EXT126DATA15170 DPI_P02 39NC83ADDR16127SDWE171 DPI_P0340VDD_
13、EXT84ADDR15128 SDRAS172 VDD_INT41VDD_INT85VDD_INT129RESET173 DPI_P0542DAI_P0686ADDR14130TMS174 DPI_P04 43DAI_P0587AMI_WR131SDCAS175 DPI_P06 44 DAI_P0988AMI_RD132VDD_INT176 GND177* * at BOTTOM 130 W9864G6KH-6 (HDMI : U1020) W9864G6KH-6 Pin description W9864G6KH Publication Release Date: Nov. 12, 2013
14、 - 4 - Revision A02 4. PIN CONFIGURATION 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 LDQM CAS RAS CS BS0 BS1 A10/AP A0 A1 A2 A3 DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 D
15、Q9 DQ8 NC UDQM CLK CKE NC A11 A9 A8 A7 A6 A5 A4 VDDQ VDDQ VSSQ VSSQ VDD VDD VSS VSSQ VSSQ VDDQ VSS VSS WE VDD VDDQ W9864G6KH Publication Release Date: Nov. 12, 2013 - 5 - Revision A02 5. PIN DESCRIPTION PIN NUMBERPIN NAME FUNCTION DESCRIPTION 23 26, 22, 29 35 A0 A11 Address Multiplexed pins for row
16、and column address. Row address: A0 A11. Column address: A0 A7. A10 is sampled during a precharge command to determine if all banks are to be precharged or bank selected by BS0, BS1. 20, 21BS0, BS1 Bank Select Select bank to activate during row address latch time, or bank to read/write during addres
17、s latch time. 2, 4, 5, 7, 8, 10, 11, 13, 42, 44, 45, 47, 48, 50, 51, 53 DQ0 DQ15 Data Input/ Output Multiplexed pins for data output and input. 19 CS Chip Select Disable or enable the command decoder. When command decoder is disabled, new command is ignored and previous operation continues. 18 Row A
18、ddress Strobe Command input. When sampled at the rising edge of the clock , CAS and WE define the operation to be executed. 17 CAS Column Address Strobe Referred to 16 WE Write Enable Referred to 39, 15 UDQM LDQM Input/output mask The output buffer is placed at Hi-Z (with latency of 2) when DQM is s
19、ampled high in read cycle. In write cycle, sampling DQM high will block the write operation with zero latency. 38 CLK Clock Inputs System clock used to sample inputs on the rising edge of clock. 37 CKE Clock Enable CKE controls the clock activation and deactivation. When CKE is low, Power Down mode,
20、 Suspend mode, or Self Refresh mode is entered. 1, 14, 27 VDD Power Power for input buffers and logic circuit inside DRAM. 28, 41, 54 VSS Ground Ground for input buffers and logic circuit inside DRAM. 3, 9, 43, 49 VDDQ Power for I/O buffer Separated power from VDD, to improve DQ noise immunity. 6, 1
21、2, 46, 52VSSQ Ground for I/O buffer Separated ground from VSS, to improve DQ noise immunity. 36, 40 NC No ConnectionNo connection. 131 W9864G6KH-6 Block diagram W9864G6KH Publication Release Date: Nov. 12, 2013 - 6 - Revision A02 6. BLOCK DIAGRAM CLK CKE A10 CLOCK BUFFER COMMAND DECODER ADDRESS BUFF
22、ER REFRESH COUNTER COLUMN COUNTER CONTROL SIGNAL GENERATOR MODE REGISTER COLUMN DECODER SENSE AMPLIFIER CELL ARRAY BANK #2 COLUMN DECODER SENSE AMPLIFIER CELL ARRAY BANK #0 COLUMN DECODER SENSE AMPLIFIER CELL ARRAY BANK #3 DATA CONTROL CIRCUIT DQ BUFFER COLUMN DECODER SENSE AMPLIFIER CELL ARRAY BANK
23、 #1 NOTE: The cell array configuration is 4096 * 256 * 16 A0 A9 BS0 BS1 CS RAS CAS WE A11 132 PCM1690 (HDMI : U1019) PCM1690 Pin Function TERMINAL I/O PULL- DOWN 5-V TOLERANT DESCRIPTION NAMEPIN RSV21Reserved, tied to analog ground RSV12Reserved, left open RSV23Reserved, tied to analog ground RSV14R
24、eserved, left open RSV25Reserved, tied to analog ground LRCK6IYesNoAudio data word clock input BCK7IYesNoAudio data bit clock input DIN18INoNoAudio data input for DAC1 and DAC2 DIN29INoNoAudio data input for DAC3 and DAC4 DIN310INoNoAudio data input for DAC5 and DAC6 DIN411INoNoAudio data input for
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