Shure_PG4_Wireless_Receiver_Service_Manual 电路图.pdf

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1、PG4 Wireless Reciever Service Manual 2006 Shure Incorporated 25A1104(Rev.1) 25A1104 PG4 WIRELESS RECEIVER PRODUCT DESCRIPTION The Shure Model PG4 is a dual conversion super heterodyne, predictive diversity, microprocessor-con- trolled UHF receiver, operating over the frequency range of 536 MHz to 86

2、5 MHz. Power is supplied to the receiver by external dc supply with country specific approvals. The PG series is Shures most basic, lowest price tier, frequency agile wireless series. This product is intended for use in low cost entry-level presentation and amateur performance markets. FEATURES Freq

3、uency agility across a wide range of frequencies (up to 12 MHz for USA models) allows flexibility to the user to continue wireless operation as the wireless spectral landscape continues to change. Predictive Diversity provides RF reliability One seven-segment LED display on the receiver to display c

4、hannel. User interface operations include: Channel Select Functions include: RF Ready Light (green LED) Bi-color LED for audio presence/peak Fixed volume audio outputs XLR and audio outputs Fixed internal Receiver Antennas RadioFans.CN 收音机爱 好者资料库 2 25A1104 (Rev.1) DETAILED DESCRIPTION Front Panel 1a

5、udio LED Indicates strength of incoming audio signal: green for normal, amber for strong, red for peak. 2ready LED Green light indicates system is ready for use. 3LED screen 4channel button Back Panel 1AC adapter jack 2Adapter cord tie-off 3XLR balanced microphone output jack 41/4” unbalanced output

6、 jack 12 34 3421 RadioFans.CN 收音机爱 好者资料库 3 25A1104 (Rev.1) CIRCUIT DESCRIPTION General block diagram description. The receiver consists of the following components: Image filters, predictive diversity circuitry, down-converter, first IF strip, SAW filter, second mixer, second IF strip, ceramic filte

7、r, detector, RSSI buffer, low pass filter, RMS detector and expander, mute circuit, balanced and unbalanced audio outputs, tonekey detection circuit, noise squelch circuit, microprocessor and several voltage regulators. The PG4 receiver has two internal antennas mounted to the circuit board via ante

8、nna connectors. RF Strip The receiver incorporates Shures patented Predictive Diversity scheme. The microprocessors A/D input is continuously monitoring buff- ered RSSI output from the TP_RSSI_A2D test point. It uses a dynamically adaptive threshold to control dual PIN diode D510, to switch between

9、the internal antennas. The received RF signal enters an image rejection helical filter (FL510). The filter FL510 in conjunction with a discrete filter post LNA attenuates the 1st LO frequency from reaching the antenna ports. The RF signal is then down-converted with IC520, an integrated receiver fro

10、nt-end chip that includes: LNA (low noise amplifier), a GaAs FET mixer, and an IF buffer stage. The 50- Ohm impedance of the mixer outputs buffer stage is matched to the SAW filter FL600. The signal enters the 1st first IF amplifier, which consists of Q603, and then it is filtered via a secondary LC

11、 filter comprised of C533, L523, C607, and C608. The second mixer is part of IC610, which also contains the 2nd IF amplifier, limiter, FM detector, and wide dynamic range RSSI circuitry. The second mixer down-con- verts the first IF signal (110.6 MHz) down to the second IF frequency of 10.7 MHz. The

12、 second IF signal is filtered with 10.7MHz ceramic filters FL620 and FL625 and then demodulated with IC610 and quadrature coil L610. The audio output from the detector chip is injected to an adjustable audio gain stage and also to the noise squelch stage. The RSSI output from the detector chip is co

13、nnected to an input of the A/D converter of the microprocessor for control of the predictive diversity circuit. Buffer LNA 1 st MIXER Helical Filter HPF for lowside injected 1st LO LPF for highside injected 1st LO 1 st LO LPF VCO From P Controller Internal Antenna A A Internal Antenna B Predictive D

14、iversity From microcontroller PIN Diode Switch To SAW filter RadioFans.CN 收音机爱 好者资料库 4 25A1104 (Rev.1) The first, the second VCOs and PLL The first VCO is a two-stage design composed of an oscillator stage and a buffer stage. Its frequency is controlled with the synthesizer chip IC1. The first stage

15、 (Q724) is a common emitter Colpitts oscillator. The air wound resonator L720 is coupled to the transistor with C723, and to the modulation varactor diode by C721. Inductor L720, capacitor C720, and trimmer CV720 form the resonant tank. Trimmer capac- itor CV720 sets the VCO tuning voltage. It is us

16、ed to tune out parts tolerances and process variances to insure adequate VCO frequency coverage. The buffer stage Q712 is a common emitter stage. It has a resonant tank at the collector that consists of L710, C730, and part of the capacitance of C729. The latter also forms an impedance matching netw

17、ork to match to the 50 Ohm input impedance of the low pass filter. The local oscillator signal is then divided into the mixer injection path C522, and the synthesizer path R706, R717 and C716. The second local oscillator consists of a single stage Colpitts oscillator (Q760). The second LO resonant t

18、ank consists of L756 and C756, and is coupled via C755 to the varactor diode D755 that receives a control voltage from the phase locked loop. Capacitor C758 couples the tank to the oscillator. The output tank and matching capacitors C762 and C763, provide 2nd LO output to the PLL chip, and via low p

19、ass filter C763, L763, C765, to the second mixer. The synthesizer chip IC1 is a dual synthesizer that consists of two dual modulus prescalers, two separate high-resolution synthesizers, a reference crystal divider, and charge pumps with selectable current levels. Y707 a 16 MHz crystal maintains the

20、frequency reference for the PLL. DC Power Supply Section The receiver works with a PS20 power supply that is connected to CON400. Diode D400 provides reverse polarity protection. RF chokes; E398, E400, E399 and E401 provide RF isolation between the power supply and the receiver. IC400 is the first v

21、oltage regulator stepping down the PS20s unregulated voltage to a constant, low ripple, 9V DC voltage used by the audio section of the receiver. The 9 V is then down regulated to 5V with IC401, to be used in the RF sections. The regulated 5V is then down regulated to 3.3V with (IC430) and used for t

22、he digital circuit blocks and pin diode switching. Audio Section The audio travels from the FM detector output (IC610 pin 7) to an adjustable gain stage (IC200-4) which is used to exactly match the audio level seen by the expander to that seen by the compressor in the transmitter. In parallel with t

23、his, a second path enters a trim stage (IC200-2) and a high-pass filter (IC200-3). This makes up the noise detection circuit. The filtered signal is rectified and averaged. The resulting dc is sent to the micro-controller (NOISE_A2D, TP_N) for squelch control. The output of IC200-4 is then split int

24、o two paths. The first path enters a crystal filter (Y285) used for tone key detection. The filtered signal is rectified and averaged. The resulting dc is sent to the micro-controller (TONEKEY_A2D, TP_TK) for tone key detection. The sec- ond path (main audio path) connects to a low-pass filter (IC20

25、0-1), used to protect the RMS detector from high frequency tone-key and RF noise. This filter is in combination with a secondary audio muting circuit (Q113) that increases the muting ability of the receiver with rail-to- rail noise present. The audio then splits down two paths: the RMS detector and

26、the VCA. The RMS detector produces a DC voltage that varies 6mV per dB of input signal. The detector output is fed to the expansion threshold stage (IC260-3). This stage provides the transition from compressed to uncompressed signal. At low levels, the audio is not expanded because D134 is turned of

27、f. As the AC level increases, the output of IC260-3 decreases enough to turn the diode on. As D134 conducts, the compression ratio changes from 1:1 to 1:5. Once D134 is turned fully on, the audio expansion ratio remains fixed at 1:5. An additional diode in the bias network (D122) provides temperatur

28、e compensation for changes in the Vy, or cut-in voltage of D134. After the expansion threshold stage, the DC control signal is attenuated by a buffer stage (IC260-4). This DC voltage is fed to the VCA control port Ec+. Ec- is fed the VREF voltage. Together these voltages determine the gain of the ex

29、pander. The audio exiting the VCA is amplified by IC260-2, and travels via the de-emphasis circuitry to the outputs. The audio peak level is determined by comparing the DC level at the output of the expansion threshold stage (AUDIO_A2D) to VREF. The signal then enters the balanced and unbalanced out

30、put stages. The balanced output is set for mic level, where mic level is 14dB down from line level. 5 25A1104 (Rev.1) RF & AUDIO BLOCK DIAGRAM From P Controller Audio & Muting Circuitry Audio ProcMuting Unbalanced Balanced 18 kHz LPF Tone Key Detector Noise Squelch Detector To uP To uP Buffer Audio

31、Outputs Buffer Buffer 2nd MIXER 110 MHz SAW Filter 2 nd LO VCO Sanyo LA8662V 2nd IF/Detector 10.7 MHz LMX2335 LTM PLL From 1 st Mixer To uP Buffer and DC gain LPF 10.7 MHz ceramic filters Audio output RSSI output RF 1st and 2nd IF 2nd mixer and detector 6 25A1104 (Rev.1) Digital Section The Freescal

32、e 8Kb FLASH microprocessor was chosen to maximize its benefits and to reduce system cost. The internal ADC converters are utilized to sample DC voltages to handle switching diversity, audio metering, audio muting, noise squelching, and tone-key detection. RF band detection uses four digital inputs.

33、In addition, the Freescale microprocessor controls the 7-segment LED display and handles the user interface channel selection. Display Circuitry 1 Software Version To verify which software version is loaded, use the following procedure: Hold the select button while plugging in the device. While cont

34、inuing to hold the select button down, the display should start flashing and sequentially read out a repeating message similar to this one: b01-15-12c0-34c0 This can be decoded as follows: b:this is a receiver software load. (a indicates a transmitter load) 01-:major version number. 15-minor version

35、 number. 12c0-software audio trim level 34c0-software predictive diversity rssi trim level ACCESSING DIFFERENT MODES NORMAL MODE UNDER USUAL USAGE CONDITIONS, THE DEVICE WILL POWER ON IN NORMAL MODE. BENCH TESTING SHOULD NOT BE DONE IN NORMAL MODE. SINCE THE ATE MODE PROVIDES A SPECIAL FREQUENCY MAP

36、, THE FREQUENCIES WILL BE DIFFERENT IN NORMAL MODE. ATE MODE A Microwire serial bus using three pins, TP_ATELE, TP_ATEDATA, and TP_ATECLK will control the ATE mode. This interface can be used to control and test all microprocessor-based functions of the board. These ATE frequencies are shown in Tabl

37、e 1 Table 1 1, 2, 3 b, c, d ATE Mode Test Frequencies (MHz) H7 K7 M7 M10 P11 Q11 R10 R11 R12 JB T10 1 Flow b 536.000 589.500 662.000674.000 702.000 740.000799.700770.000 794.000 806.000854.000 2 Fmid c 542.000 594.500 668.000681.500 708.000 746.000806.000777.000 799.700 808.000859.500 PG4 3 Fhigh d

38、548.000 602.000 674.000686.000 714.000 751.700812.000781.700 806.000 809.850864.800 7 25A1104 (Rev.1) RF BAND RESISTORS Four resistors Ra, Rb, Rc, and Rd are responsible to start the microcontroller in a RF band. Table 2 shows the reference designators and how the voltages at the test points reflect

39、 the operating RF band. . Table 3 shows the variant resistor installation options for each band. When a resistor is installed the microprocessor will read a logic low, otherwise it will read a logic high. Table 2 PG4 Reference Designators Rd Rc Rb Ra R316 R315 R314 R313 Table 3 RF BAND Board ID Rd R

40、c Rb Ra H7 A K7 B Installed M7 C Installed M10 D Installed Installed P11 E Installed Q11 F Installed Installed R10 G Installed Installed R11 H Installed Installed Installed R12 J Installed JB K Installed Installed T10 L Installed Installed Reserved M Installed Installed Installed Reserved N Installe

41、d Installed 8 25A1104 (Rev.1) Microcontroller Netnames and Programming Testpoint List PinPort Name Testpoint 1 RESETn Reset TP_RST 2 PTC0/TxD2 Seven Segment A 3 PTC1/RxD2 Seven Segment B 4 PTC2/SDA1 Seven Segment C 5 PTC3/SCL1 Seven Segment D 6 PTC4 Seven Segment E 7 PTC5 Seven Segment F 8 PTC6 Seve

42、n Segment G 9 PTC7 NC 10 PTE0/TxD1 Select Button 11 PTE1/RxD1 NC 12 IRQ NC 13 PTE2/SS1n Ra 14 PTE3/MISO1 Rb 15 PTE4/MOSI1 Rc 16 PTE5/SPSCK1 Rd 17 VSS1 EGND 18 VSS2 EGND 19 VDD +3.3Vdd 20 PTD0/TPM1CH0RF LED 21 PTD1/TPM1CH1 Red LED (Active High) 22 PTD2/TPM1CH2Green LED (Active High) 23 PTD3/TPM2CH0AN

43、T_A 24 PTD4/TPM2CH1ANT_B 25 PTB0/AD1P0 NOISE_A2D 26 PTB1/AD1P1 TONEKEY_A2D 27 PTB2/AD1P2 RSSI_A2D 28 PTB3/AD1P3 AUDIO_A2D 29 PTB4/AD1P4 NC 30 PTB5/AD1P5 NC 31 PTB6/AD1P6 NC 32 PTB7/AD1P7 NC 33 VREFH +3.3Vdd 34 VREFL EGND 35 PTA0/nKBI1P0 CLOCK 36 PTA1/nKBI1P1 DATA 37 PTA2/nKBI1P2 LE 38 PTA3/nKBI1P3 A

44、UDIO_MUTE 39 PTA4/nKBI1P4 NC 40 PTA5/nKBI1P5 TP_ATECLK 41 PTA6/nKBI1P6 TP_ATEDATA 42 PTA7/nKBI1P7 TP_ATELE 43 VDDAD +3.3Vdd 44 VSSAD EGND 45 PTG0/BKGD/MS TP_BKGD 46 PTG1/XTAL Crystal 47 PTG2/EXTAL Crystal 48 PTG3 PLL_LD 9 25A1104 (Rev.1) The microprocessor reads the RSSI level from an ADC several ti

45、mes a second when the PG4 is unmuted, to predict if a switch is neces- sary to avoid an audible dropout. Thresholds were calculated from the above RSSI curve. PG4 RSSI Curve 0.5 1 1.5 2 2.5 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 RF Level TP_RSSI Vdc Series1 10 25A1104 (Rev.1) NOTES 11 25A110

46、4 (Rev.1) FUNCTIONAL TEST GENERAL INFORMATION LOOKUP TABLE REQUIRED TEST EQUIPMENT (OR APPROVED EQUIVALENT OR SUPERIOR MODELS): LISTENING TEST Before completely disassembling the receiver, operate it to determine whether it is functioning normally and try to duplicate the reported malfunction. Refer

47、 to pages 2 and 3 for operating instructions, troubleshooting, and specifications. Review any customer complaint or request, and focus the listening test on any reported problem. The following, more ex- tensive, functional tests require partial disassembly. FUNCTIONAL TEST NOTE: for these tests a to

48、nekey generator must be used. If none is available, the unit must be opened and the tone key must be disabled. 1.Apply +12 Vdc to the power input of the receiver (PS20). 2.Set up the Audio Analyzer as follows: Engage A-weighting filter Engage 30kHz LPF filter 3.Set up RF signal generator as follows:

49、 Frequency = Fo (refer to the frequency tables on page 21) Amplitude = 0 dBm radiated FMrate = 1kHz Deviation = (see table next page) RF Signal GeneratorAgilent E4420B Audio AnalyzerHP 8903B Power SupplyPS20 BNC (M) to BNC (M) cable (2)Shure PT1838A BNC (F) to 1/4” adapterShure PT1838C Matching UA820 AntennaFrequency Dependent BandLowHighLowHigh1st LO2nd LO H7536548757.2769.2Fc+110.699.9MHz K7590602811.2823.2Fc+110.699.9MHz M7662674883.2