JVC-XVM50BK-cd-sup 电路图 维修手册.pdf

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1、SERVICE MANUAL COPYRIGHT 2002 VICTOR COMPANY OF JAPAN, LTD. No.A0008B 2002/11 XV-M50BK DVD VIDEO PLAYER A0008B200211 XV-M50BK TABLE OF CONTENTS 1Description of major ICs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2、2 2Block diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Area Suffix J - U.S.A. C - Canada Because service manual XV-M50BK (Issue No.A0008) which has already been issued contains some mistakes,

3、 the following pages are modified in this service manual. *Description of major ICs *Block diagrams Refer to the service manual XV-M50BK (Issue No. A0008) which has already been issued for other pages. Supplement RadioFans.CN 收音机爱 好者资料库 XV-M50BK 2 SECTION 1 Description of major ICs 1.1 AK93C65AF-X (

4、IC403) : EEPROM Pin layout Block diagram Pin function NOTE : The pull-up resistor of the PE pin is about 2.5Mohm (VCC=5V) Pin no.SymbolFunction 1PE Program enable (With built-in pull-up resistor) 2VCCPower supply 3CSChip selection 4SKCereal clock input 5DICereal data input 6DOCereal data output 7GND

5、Ground 8NCNo connection RadioFans.CN 收音机爱 好者资料库 XV-M50BK 3 1.2 AN8702FH(IC101):Frontend processor Pin layout Pin function Pin No.SymbolI/ODescription 1PC1IInput for Laser current monitor 2PC01OLaser power control output for DVD 3PC2IPhoto detector fo CD 4PC02OLaser power control output for CD 5TGBAL

6、ITangential phase balance control terminal 6TBALITracking balance control terminal 7FBALIFocus balance control ter 8POFLTOTrack detection threshold level terminal 9DTRDIData slice part data read signal input terminal (For RAM) 10IDGTIData slice part address part gate signal input terminal (For RAM)

7、11STANDBYIStandby mode control terminal 12SENISEN(Serial data input terminal) 13SCKISCK(Serial data input terminal) 14STDIISTDI(Serial data input terminal) 15RSELIDVD and CD selection 16JLINEIJ-line setting output (FEP) 17TENITracking error output amplifier reversing input terminal 18TEOUTOTracking

8、error signal output terminal 19ASNIOff set adjustment terminal for DRC 20ASOUTOAll added signal output terminal 21FENIFocus error output amplifier reversing input terminal 22FEOUTOFocus error signal output terminal 23VSS-Connect to GND 24TGOTangential phase error signal output terminal 25VDD-Power s

9、upply terminal 3V 26GND2-Connect to GND 27VREF2OVREF2 voltage output terminal 28VCC2-Power supply terminal 5V 29VHALFOVHALF voltage output terminal 30DFLTONOFilter amplifier reversing output terminal 31DFLTOPOFilter amplifier output terminal 32DSFLTOConnected capacitor terminal for filter output 33G

10、ND3-Connect to GND 34RFDIFOORF operation output terminal 35RFOUTORF output terminal 36VCC3-Power supply terminal 5V 37RFCIFilter for RF amplifier RadioFans.CN 收音机爱 好者资料库 XV-M50BK 4 38DCRFOAll addition amplifier capacitor terminal 39OFTROOFTR output teminalr 40BDOOBDO output terminal 41RFENVORF envel

11、ope output terminal 42BTTOMOBottom envelope detection filter terminal 43PEAKOPeak envelope detection filter terminal 44AGCGOAGC amplifier gain control teminalr 45AGCOOAGC amplifier level control terminal 46TESTSGITEST signal input terminal 47RFINPIRF signal positive input terminal 48RFINNIRF signal

12、negative input terminal 49VIN5IRF input of external division into 4 terminal for CD 50VIN6IRF input of external division into 4 terminal for CD 51VIN7IRF input of external division into 4 terminal for CD 52VIN8IRF input of external division into 4 terminal for CD 53VIN9IRF input of external division

13、 into 2 terminal for DVD 54VIN10IRF input of external division into 2 terminal for DVD 55VCC1-Power supply terminal 5V 56VREF1OVREF1 voltage output terminal 57VIN1IExternal division into four (DVD/CD) RF input terminal1 58VIN2IExternal division into four (DVD/CD) RF input terminal2 59VIN3IExternal d

14、ivision into four (DVD/CD) RF input terminal3 60VIN4IExternal division into four (DVD/CD) RF input terminal4 61GND1-Connect to GND 62VIN11I3 beem sub input terminal for CD 63VIN12I3 beem sub input terminal for CD 64HDTYPEIHD type switching Pin No.SymbolI/ODescription XV-M50BK 5 1.3 HY57V161610DTC8(I

15、C504,IC505) : 16MB SDRAM Block diagram Pin function Pin No.SymbolDescription 1VCCPower supply 2,3DQ0,1Data input/output 4VSSConnect to GND 5,6DQ2,3Data input/output 7VDDPower supply 8,9DQ4,5Data input/output 10VSSConnect to GND 11,12DQ6,7Data input/output 13VCCPower supply 14LDQMLower DQ mask enable

16、 15 WE Write enable 16 CAS Column address strobe 17 RAS Row address strobe 18 CS Chip enable 19,20A11,10Address inputs 2124A03Address inputs 25VCCPower supply 26VSSConnect to GND 2732A49Address inputs 33NCNon connect 34CKEClock enable 35CLKSystem clock input 36UDQMUpper DQ mask enable 37NCNon connec

17、t 38VCCPower supply 39,40DQ8,9Data input/output 41VSSConnect to GND 42,43DQ10,11Data input/output 44VDDPower supply 45,46DQ12,13Data input/output 47VSSConnect to GND 48,49DQ14,15Data input/output 50VSSConnect to GND XV-M50BK 6 1.4 M35500AFP(IC802) : FL Driver Pin layout Pin function Pin No.SymbolI/O

18、Description 1VDD-Power supply terminal 2XOUTOThe short-circuit is made and the capacitor is connected with XIN on the outside 3VSS-Connect to ground 4XINIThe short-circuit is made and the capacitor is connected with XOUT on the outside 5RESETIReset input L:Reset 611AIN50IKey control signal input 12C

19、SIChip select input L:The serial transfer is possible 13SINISerial data input 14SOUTOSerial data output 15SCLKIClock input of serial transfer 16,17VEE-The voltage supplied to the pull down resistance is impressed 1820DISC31 INDOIndicator control signal output of disc indicator 13 21,22NC-Not use 232

20、97G1GOFL Grid control signal output 3043S14S1OFL Segment control signal output 44VDD-Power supply terminal XV-M50BK 7 1.5 M56788FP-W (IC271) : Traverse mechanism driver Terminal Layout Block diagram XV-M50BK 8 1.6 MN101C49GGJ1(IC701): System controller Terminal layout Pinfunction Pin No.SymbolI/OFun

21、ction 1GND-Connect to ground 2NC-No connect 3NC-No connect 4NC-No connect 5NTSELINTSC/PAL selection 6POWER SWIPower switch detect terminal 7SHUT1-Connect to VDD 8KEY1-5-Connect to VDD 9KEY6-10-Connect to VDD 10VREF+IReference voltage 11VDDIPower supply 12OSC2OExternal terminal for connected oscirato

22、r 13OSC1IExternal terminal for connected oscirator 14VSS-Connect to ground 15XI-Connect to ground 16XO-No connect 17MMOD-Connect to ground 18DADATAI/OData bus for DAC 19DACSOOSerial bus output for DAC 20DACKI/OClock for DAC 21S2UDTOCommunication between unit microcomputers DATA output 22U2SDTICommun

23、ication between unit microcomputers DATA output 23SCLKI/OSerial clock bus 24BUSYI/OBusy bus 25CPURSTOUnit microcomputer reset 26REQICommnication between unit microcomputers REQ 27REMOIRemote control interrruption 28-Non connect 29-Non connect 30-Connect to ground 31-Connect to ground 32-Connect to g

24、round 33RESETIDVD reset 34-No connect 35-No connect 36VCD-No connect 37OSDCK-No connect 38NT-No connect 39FS2-No connect XV-M50BK 9 40CHREQIChanger commnication REQUEST 41CHSTOChanger commnication STROBE 42CHDATAOChanger commnication DATA I/O 43-No connect 44CHCKIChannel clock 45FLDATAOOSerial data

25、output 46FLDATAIISerial data input 47FLCKOClock output of serial transfer 48FLCSOChip select output 49FLRSTOReset output 50EEDOOData output to EEPROM 51EEDIIData input from EEPROM 52EECKOClock signal output to EEPROM 53EECSOChip select output to EEPROM 54VS1OFanction SW control 55VS3OFanction SW con

26、trol 56DMUT1-No connect 57DMUT2-No connect 58PDB2-No connect 59PDB1-No connect 60DEMP2-No connect 61DEMP1-No connect 62DENA-No connect 63KARAOKEOKARAOKE Mode switching terminal 64POWER ONOPower on control output 65VS2-No connect 66-No connect 67-No connect 68-No connect 69-No connect 70-No connect 7

27、1-No connect 72-No connect 73-No connect 74-No connect 75-No connect 76-No connect 77AVCIIAV compulink signal input 78AVCOOAV compulink signal output 79RGBORGB select control signal output 80STDINDOStandby LED control signal output 81-No connect 82-No connect 83-No connect 84-No connect 85-No connec

28、t 86CS4-No connect 87MA-No connect Pin No.SymbolI/OFunction XV-M50BK 10 88MB-No connect 89M1M3-No connect 90MD-No connect 91MC-No connect 92GAIN2-No connect 93GAIN1-No connect 94HPMUT-No connect 95DAVSS-No connect 96LMUTE-No connect 97CMUTE-No connect 98SMUTE-No connect 99MUTEOMuting control signal

29、output 100DAVDD-Power supply terminal Pin No.SymbolI/OFunction XV-M50BK 11 1.7 MN102L62GGP (IC401) : Unit CPU PinNo.SymbolI/OFunction 1WAITIMicon wait signal input 2REORead enable 3SPMUTEOSpindle muting output to IC251 4WENOWrite enable 5CS0-Not use 6CS1OChip select for ODC 7CS2OChip select for ZIVA

30、 8CS3OChip select for outer ROM 9DRVMUTEODriver mute 10SPKICK-Non connect 11LSIRSTOLSI reset 12WORDIBus selection input 13A0OAddress bus 0 for CPU 14A1OAddress bus 1 for CPU 15A2OAddress bus 2 for CPU 16A3OAddress bus 3 for CPU 17VDD-Power supply 18SYSCLK-Non connect 19VSS-Ground 20XI-Not use (Conne

31、ct to vss) 21XO-Non connect 22VDD-Power supply 23OSCIIClock signal input(13.5MHz) 24OSCOOClock signal output(13.5MHz) 25MODEICPU Mode selection input 26A4OAddress bus 4 for CPU 27A5OAddress bus 5 for CPU 28A6OAddress bus 6 for CPU 29A7OAddress bus 7 for CPU 30A8OAddress bus 8 for CPU 31A9OAddress bu

32、s 9 for CPU 32A10OAddress bus 10 for CPU 33A11OAddress bus 11 for CPU 34VDD-Power supply 35A12OAddress bus 12 for CPU 36A13OAddress bus 13 for CPU 37A14OAddress bus 14 for CPU 38A15OAddress bus 15 for CPU 39A16OAddress bus 16 for CPU 40A17OAddress bus 17 for CPU 41A18OAddress bus 18 for CPU 42A19OAd

33、dress bus 19 for CPU 43VSS-Ground 44A20OAddress bus 20 for CPU 45TXSELOTX Select 46HAGUPOConnect to pick-up 47CD/DVDICD/DVD Detect signal 48ADPDOPower down control signal to IC511 49HMFONOHFM Control output to IC102 50TRVSWIDetection switch of traverse inside 51FGINIFocus gain input 52TRS 53ADSCENOS

34、ervo DSC serial I/F chip select 54VDD-Power supply 55FEPENOSerial enable signal for FEP 56SLEEPOStandby signal for FEP 57BUSYICommunication busy 58REQOCommunication request 59CIRCENOCIRC serial I/F chip select 60HSSEEK 61VSS-Ground 62EPCSOEEPROM chip select 63EPSKOEEPROM clock 64EPDIIEEPROM data inp

35、ut 65EPDOOEEPROM data output 66VDD-Power supply 67SCLKOOCommunication clock 68S2UDTICommunication input data 69U2SDTOCommunication output data 70CPSCKOClock for ADSC serial 71SDINIADSC serial data input 72SDOUTOADSC serial data output 73-INot use (Pull up) 74-INot use (Pull up) 75NMIINMI Terminal 76

36、ADSCIRQIInterrupt input of ADSC 77ODCIRQIInterrupt input of ODC 78DECIRQIInterrupt input of ZIVA 79WAKEUP-Connect to ground 80ODCIRQ2IInterruption of system control 81ADSEPIAddress data selection input 82RSTIReset input 83VDD-Power supply 84TEST1ITest signal 1 input 85TEST2ITest signal 2 input 86TES

37、T3ITest signal 3 input 87TEST4ITest signal 4 input 88TEST5ITest signal 5 input 89TEST6ITest signal 6 input 90TEST7ITest signal 7 input 91TEST8ITest signal 8 input 92VSS-Ground 93D0I/OData bus 0 of CPU 94D1I/OData bus 1 of CPU 95D2I/OData bus 2 of CPU 96D3I/OData bus 3 of CPU 97D4I/OData bus 4 of CPU

38、 98D5I/OData bus 5 of CPU 99D6I/OData bus 6 of CPU 100D7I/OData bus 7 of CPU PinNo.SymbolI/OFunction XV-M50BK 12 1.8 MN103S13BDA(IC301):Optical disc controller Pin layout Block diagram XV-M50BK 13 Pin function PinNo.SymbolI/ODescription 1HDD15I/OATAPI Data 2HDD0I/OATAPI Data 3HDD14I/OATAPI Data 4VDD

39、-Power supply 3V 5HDD1I/OATAPI Data 6HDD13I/OATAPI Data 7HDD2I/OATAPI Data 8VSS-Connect to GND 9HDD12I/OATAPI Data 10VDD-Power supply 2.7V 11HDD3I/OATAPI Data 12HDD11I/OATAPI Data 13HDD4I/OATAPI Data 14HDD10I/OATAPI Data 15VDD-Power supply 3V 16HDD5I/OATAPI Data 17HDD9I/OATAPI Data 18VSS-Connect to

40、GND 19HDD6I/OATAPI Data 20HDD8I/OATAPI Data 21HDD7I/OATAPI Data 22VDDH 23NRESETIATAPI Reset input 24MASTERI/OATAPI Master/slave select 25NINT0OInterruption of system control 0 26NINT1OInterruption of system control 1 27WAITDOCOWait control of system control 28NMRSTOReset of system control (Connect t

41、o TP302) 29DASPSTISetting of initial value of DASP signal 30VDD-Power supply 3V 31OSCO2ONon connect 32OSCI2INon connect 33UATASELIConnect to VSS 34VSS-Connect to GND 35PVSSDRAMConnect to VSS 36PVDDDRAMConnect to VDD(2.7V) 37CPUADR17ISystem control address 38CPUADR16ISystem control address 39VSS-Conn

42、ect to GND 40CPUADR15ISystem control address 41CPUADR14ISystem control address 42CPUADR13ISystem control address 43CPUADR12ISystem control address 44VDD-Power supply 2.7V 45CPUADR11ISystem control address 46CPUADR10ISystem control address 47CPUADR9ISystem control address 48CPUADR8ISystem control add

43、ress XV-M50BK 14 49CPUADR7ISystem control address 50CPUADR6ISystem control address 51CPUADR5ISystem control address 52CPUADR4ISystem control address 53CPUADR3ISystem control address 54CPUADR2ISystem control address 55CPUADR1ISystem control address 56VSS-Connect to GND 57CPUADR0ISystem control addres

44、s 58NCSISystem control chip select 59NWRIWriting system control 60NRDIReading system control 61VDD-Power supply 3V 62CPUDT7I/OSystem control data 63CPUDT6I/OSystem control data 64PVPPDRAMOConnect to VSS 65PTESTDRAMIConnect to VSS 66PVDDDRAMConnect to VDD(2.7V) 67PVSSDRAMConnect to VSS 68CPUDT5I/OSys

45、tem control data 69CPUDT4I/OSystem control data 70CPUDT3I/OSystem control data 71VSS-Connect to GND 72CPUDT2I/OSystem control data 73CPUDT1I/OSystem control data 74CPUDT0I/OSystem control data 75CLKOUT1OClock signal output (16.9/11.2/8.45MHz) 76VDD-Power supply 3V 77TEHLDOMirror gate (Connect to TP1

46、41) 78DTRDOData frequency control switch (Connect to TP304) 79IDGTOCAPA switch 80BDOIRF Dropout/BCA data 81CPDET2IOuter capacity detection 82CPDET1IInner capacity detection 83VSS-Connect to GND 84MMODIConnect to VSS 85NRSTISystem reset 86VDD-Power supply 3V 87CLKOUT2OClock 16.9MHz 88SBCK/PLLOKOFlame

47、 mark detection 89IDOHOLDOID gate for tracking holding 90JMPINHOJump prohibition 91LGOLand/group switch 92NTRONITracking ON 93DACDATAOSerial data output (Connect to TP148) 94DACLRCKOIdentification signal of L and R (Connect to TP149) 95DACCLKIClock for serial data output 96IPFLAGIInput of IP flag Pi

48、nNo.SymbolI/ODescription XV-M50BK 15 97BLKCKISub code/block/input clock 98LRCKIIdentification signal of L and R (Connect to VSS) 99VSS-Connect to GND 100OSCI1IOscillation input terminal 16.9MHz 101OSCO1OOscillation output terminal 16.9MHz 102VDD-Power supply 3V 103PVSS-Connect to GND 104PVDD-Power s

49、upply 3V 105P1I/OTerminal master polarity switch input 106P0I/OCIRC-RAM,OVER/UNDER Interruption 107VSS-Connect to GND 108SBCKOClock output for sub code,serial input 109SUBCISub code,serial input 110NCLDCKISub code,flame clock input 111CHCK40IClock is read to D 112DAT3IAT30 (Output of division frequency from ADSC) 113DAT2IData is read from disc (Going side by side output from ADSC) 114DAT1IData is read from disc (Going side by side output from ADSC) 115DAT0IData is read from disc (Going side by side output from ADSC) 116VDD-Data is read