Marantz-UD7007v5-sacd-sm 电路图 维修手册.pdf

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1、START:|g1cz3Z09ximWbk6cjE4rRA=|ayU09y6xYkP8R20GVe2xtAwYGfEges0SOyv9QDgIs80=|bzK1xj2aIclqATWPkJDTOw=|:END Service Manual Some illustrations using in this service manual are slightly different from the actual set. Please use this service manual with referring to the operating instructions without fail

2、. For purposes of improvement, specifications and design are subject to change without notice. SUPER AUDIO CD/ BLU-RAY DISC PLAYER UD7007 /N1SG/N1B U1B/K1B/S1B UD7007 S0674-1V05DM/DG1304Copyright 2013 D 12 cm, 1 side, 2 layers (2) DVD-Video / DVD-Audio disc : 12 cm, 1 side, 1 layer; 12 cm, 1 side, 2

3、 layers / 12 cm, 2 sides, 2 layers (1 side, 1 layer) 8 cm, 1 side, 1 layer; 8 cm, 1 side, 2 layers / 8 cm, 2 sides, 2 layers (1 side, 1 layer) (3) Super Audio CD : 12 cm, 1 layer / 12 cm, 2 layer / 12 cm, Hybrid (4) Compact Disc (CD-DA) : 12 cm / 8 cm disc (5) Memory device : USB memory device (USB

4、2.0) HDMI output : Output terminal : 19-pin HDMI terminals, 2 set (Deep Colour, Dolby Digital Plus, Dolby TrueHD, DTS-HD, 3D) Analog audio output : 2 channels output terminal : Pin jack, 1 set Output level : 2 Vrms (10 k) 2 channels output terminal : Balanced terminal, 1 set Output level : 4 Vrms (1

5、0 k) Audio output characteristics : (1) Frequency response q BD (Linear PCM) : 2Hz 22kHz (48kHz sampling) : 2Hz 44kHz (96kHz sampling) : 2Hz 88kHz (192kHz sampling) w DVD (Linear PCM) : 2Hz 22kHz (48kHz sampling) : 2Hz 44kHz (96kHz sampling) : 2Hz 88kHz (192kHz sampling) e Super Audio CD : 2Hz 40kHz

6、 r CD : 2Hz 20kHz (2) S/N ratio : 125dB (BD) (3) Total harmonic distortion : 1kHz, 0.0008% (BD) (4) Dynamic range : 110dB (BD) Digital audio output : Coaxial digital output : Pin jack, 1 set n General Power supply : AC 120 V, 60 Hz Power consumption : 25W 0.3 W (Energy Saving Standby) 0.5 W (Normal

7、Standby) 14 W (Quick Start) DIMENSION 11 47/64 (298.0) 12 7/64 (307.5) 2 11/32 (59.5) 7 9/16 (192.0) 1 53/64 (46.5) 23/32 (18.2) 3 37/64 (91.0) 4 19/64 (109.2) 17 21/64 (440.0) 5 5/16 (135.0) 13 25/64 (340.0) 2 13/64 (56.0) 1 31/32 (50.0) 1 31/32 (50.0) 5 1/8 (130.0) 5/32 (4.0) 7/32 (5.5) 9 CAUTIONS

8、 IN SERVICING Initializing BD player BD player initialization should be performed when the com, peripheral parts of com, and MAIN PCB. were replaced. 1. Turn on this models power. NO DISC is displayed on the FL tube. 2. Press the this models 1 and 9 buttons simultaneously. INITIALIZING is displayed

9、on the FL tube. 3. The display on the FL tube switches to INITIALIZED, the NO DISC display reappears and initialization is completed. Service tools Measuring Disc: CD/TCD-784 DVD/VT502 or TDV-520A BD/ABD-520 or BLX-108 z Refer to MEASURING METHOD AND WAVEFORMS. When you repair the BD MECHA UNIT, you

10、 can use the following JIG. Please order to Marantz Official Service Distributor in your region if necessary. Do not supply it : 232C (TTL) USB conversion jig (Model: DUT-06635 by GeeeTech) : 1 Set Part No. : 61205000300AS : 4P RE-PH CONN CORD (1000mm) : 1 Set z Refer to HOW TO REPLACE THE MAIN PCB

11、for DVD/CD, within 12 mA of the initial value. The following two parts are specified as service parts for the MECHA UNIT. 1. MAIN PCB active low MSEL3II2C/SPI select(2); active low SPI select RST14IReset(2); active low (1)Schmitt-trigger input, 5-V tolerant. (2)Schmitt-trigger input, 5-V tolerant. (

12、3)Schmitt-trigger input and output. 5-V tolerant input. In I2C mode, this pin becomes an open-drain 3-state output; otherwise, this pin is a CMOS output. (4)Schmitt-trigger input and output. 5-V tolerant input and CMOS output. 80 PCM1795 SLES248MAY Table 1. TERMINAL FUNCTIONS (continued) TERMINAL NA

13、MENO.I/ODESCRIPTION SCK7ISystem clock input(2) VCC123Analog power supply, 5 V VCC2L28Analog power supply (left channel DACFF), 5 V VCC2R15Analog power supply (right channel DACFF), 5 V VCOML22Left channel internal bias decoupling pin VCOMR21Right channel internal bias decoupling pin VDD9Digital powe

14、r supply, 3.3 V ZEROL1I/OZero flag for left channel(4) ZEROR2I/OZero flag for right channel(4) 81 CS8966 (U23) CS8966F PQFP-44 PGAVMID / P3.7 / SPICLK RXVDD P2.4 / T2EX / CMPD 34 1 P1.4 / SWC2 P1.5 / SWC3 P3.0 / CEX2 / SWA1 / CMPA P3.1 / CEX3 / SWA2 / CMPA P3.4 / SS P1.2 / SDA / SWC0 P2.5 / T2 / CMP

15、C PGAOUT1 / P3.2 / CEX4 PGAIN1 / P3.3 / CEX5 P4.2 / SWB3 P2.2 / TXD1 P2.6 / CMPB P2.7 / CMPA / SWA0 RSTN P1.1 / ADD4 / CEX1 P1.0 / ADD3 / CEX0 P0.7 / RXD0 / ADD2 P0.6 / TXD0 / ADD1 P0.0 / PINT1.0 / ADA1 P2.3 / RXD1 P2.1 / XOUT P2.0 / XIN P1.7 / T0 / SWB0 / PINT0.1 P1.6 / T1 / SWB1 / PINT0.0 P1.3 / S

16、CL / SWC1 PGAOUT2 / P3.5 / MOSI P4.3 / SCL2 P4.1 / SDA2 VSS PGAIN2 / P3.6 / MISO P0.5 / PINT1.5 / ADC2 P0.4 / PINT1.4 / ADC1 P0.3 / PINT1.3 / ADB2 P0.1 / PINT1.1 / ADA2 P4.0 / CEC VDD VDD25 P0.2 / PINT1.2 / ADB1 RXIN RXOUT VSS 44 35 36 37 38 39 40 41 42 43 23 24 25 26 27 28 29 30 31 32 33 2 3 4 5 6

17、7 8 9 10 11 22 21 20 19 18 17 16 15 14 13 12 CS8966 (MAIN PCB U21) 82 PIN DESCRIPTION NIP.oN NIP EPYT EMAN NIP FUNCTION DESCRIPTION Port 3.7 GPIO 8051 P3.7 GPIO. SPICLK It behaves as the Master clock output (Master Mode), or Slave clock input (Slave Mode) of the on-chip SPI interface. PGAVMID P3.7 I

18、/O, A 1 PGA VMID output. Port 3.6 GPIO 8051 P3.6 GPIO. MISO It behaves Master data Input of the on-chip SPI interface (Master Mode), or Slave data Output of the SPI interface (Slave Mode). PGAIN2 P3.6 I/O, A 2 PGA IN2. Port 3.5 GPIO 8051 P3.5 GPIO. MOSI It behaves Master data Output of the on-chip S

19、PI interface (Master Mode), or Slave data Input of the SPI interface (Slave Mode). PGAOUT2 P3.5 I/O, A 3 PGA OUT2. Port 2.3 GPIO 8051 P2.3 GPIO. RXD1 P2.3 I/O 4 This pin also can be configured as RXD of UART 1. Port 2.2 GPIO 8051 P2.2 GPIO. TXD1 P2.2 I/O 5 This pin also can be configured as TXD of U

20、ART 1. Port 2.1 GPIO 8051 P2.1 GPIO. To allow proper operation as GPIO P2.1 function, crystal oscillator must be disabled by setting XOSCCFG register to 0 x00. XOUT Crystal Oscillator Output P2.1 I/O, A 6 This pin also can be configured as XOUT for crystal oscillator. XOUT is in parallel connection

21、with the GPIO pin. To enable this pin as XOUT, the IOCFGP2.1 must be cleared to 0 x00. Port 2.0 GPIO 8051 P2.0 GPIO. To allow proper operation as GPIO P2.0 function, crystal oscillator must be disabled by setting XOSCCFG register to 0 x00. XIN Crystal Oscillator Input P2.0 I/O, A 7 This pin also can

22、 be configured as XIN for crystal oscillator. XIN is in parallel connection with the GPIO pin. To enable this pin as XIN, the IOCFGP2.0 must be cleared to 0 x00. 83 NIP.oN NIP EPYT EMAN NIP FUNCTION DESCRIPTION Port 4.1 GPIO 8051 P4.1 GPIO. SDA2P4.1 I/O, A 8 This pin also can be configured as the SD

23、A signal of the 2nd I2C slave controller. In this operation mode, this pin should also be configured as bi-directional I/O with open- drain output. 8051 P4.0 GPIO 8051 P4.0 GPIO. CEC CEC Controller input/output pin. P4.0 I/O 9 The falling edge can wake up this device from STOP mode. Port 4.7 GPIO P4

24、.7 I/O - 8051 P4.7 GPIO. Port 3.4 GPIO 8051 P3.4 GPIO. SS P3.4 I/O 10 This pin also can be configured as selecting pin which can set the on-chip SPI interface work under Master mode or Slave mode. To set the SPI interface of this device work under Slave mode, the user can connect this pin to VSS, or

25、 to a CEB output from other SPI master. To set the SPI interface of this device work under Master mode, just tie this pin to VDD. Port 4.3 GPIO 8051 P4.3 GPIO. SCL2 P4.3 I/O 11 This pin also can be configured as the SCL signal of the 2nd I2C slave controller. This pin should be configured as input o

26、nly. VSS Power 12 Ground Voltage. 0V RXVDD Power 13 VDD for RTC Supply voltage range: 1.02.75V. RXIN RXIN I, A 14 Crystal IN for RTC oscillator. RXOUT RXOUT O, A 15 Crystal OUT for RTC oscillator. Port 4.2 GPIO 8051 P4.2 GPIO. SWB3 P4.2 I/O, A 16 This pin also serves as one of the connection for ana

27、log switch B. The control of the analog switch is done by setting of ANEN of IOCFGP4.2. Port 4.4 GPIO 8051 P4.4 GPIO. SWB2 P4.4 I/O, A - This pin also serves as one of the connection for analog switch B. The control of the analog switch is done by setting of ANEN of IOCFGP4.4. 84 CS8966 Preliminary

28、NIP.oN NIP EPYT EMAN NIP FUNCTION DESCRIPTION Port 1.7 GPIO 8051 P1.7 GPIO. PINT0.1 This pin also can be configured as the expanded INT0 interrupt. T0 Timer 0 Input This pin also can be configured as Timer 0 input. SWB0 P1.7 I/O, A 17 This pin also serves as one of the connection for analog switch B

29、. The control of the analog switch is done by setting of ANEN of IOCFGP1.7. Port 1.6 GPIO 8051 P1.6 GPIO. PINT0.0 This pin also can be configured as the expanded INT0 interrupt. T1 Timer 1 Input This pin also can be configured as Timer 1 input. SWB1 P1.6 I/O, A 18 This pin also serves as one of the

30、connection for analog switch B. The control of the analog switch is done by setting of ANEN of IOCFGP1.6. Port 1.5 GPIO 8051 P1.5 GPIO. SWC3 P1.5 I/O, A 19 This pin also serves as one of the connection for analog switch B. The control of the analog switch is done by setting of ANEN of IOCFGP1.5. Por

31、t 1.4 GPIO 8051 P1.4 GPIO. SWC2 P1.4 I/O, A 20 This pin also serves as one of the connection for analog switch B. The control of the analog switch is done by setting of ANEN of IOCFGP1.4. Port 1.3 GPIO 8051 P1.3 GPIO. SCL This pin also can be configured as the SCL signal of the I2C master or I2C sla

32、ve controller. In I2C master mode, this pin should be configured as open-drain output. In I2C slave, this pin should be configured as input only. SWC1 P1.3 I/O, A 21 This pin also serves as one of the connection for analog switch B. The control of the analog switch is done by setting of ANEN of IOCF

33、GP1.3. Port 1.2 GPIO 8051 P1.2 GPIO. SDA This pin also can be configured as the SDA signal of the I2C master or I2C slave controller. In this operation mode, this pin should also be configured as bi-directional I/O with open-drain output. SWC0 P1.2 I/O, A 22 This pin also serves as one of the connec

34、tion for analog switch C. The control of the analog switch is done by setting of ANEN of IOCFGP1.2. 85 NIP.oN NIP EPYT EMAN NIP FUNCTION DESCRIPTION Port 4.5 GPIO 8051 P4.5 GPIO. SWC5 P4.5 I/O, A - This pin also serves as one of the connection for analog switch C. The control of the analog switch is

35、 done by setting of ANEN of IOCFGP4.5. Port 1.1 GPIO 8051 P1.1 GPIO. CEX1 PCA CCAP Module 1 This pin also can be configured as CEX pin for PCA CCP module 1. CEX is an I/O interface signal for compare/capture input and PWM output. ADD4 P1.1 I/O, A 23 This pin also can be configured as the input to th

36、e ADC channel D by setting ANEN of IOCFGP1.1 to 1. Only one of ADD1, ADD2, ADD3 and ADD4 can be enabled at any one time. Port 1.0 GPIO 8051 P1.0 GPIO. CEX0 PCA CCAP Module 0 This pin also can be configured as CEX pin for PCA CCP module 0. CEX is an I/O interface signal for compare/capture input and

37、PWM output. ADD3 P1.0 I/O, A 24 This pin also can be configured as the input to the ADC channel D by setting ANEN of IOCFGP1.0 to 1. Only one of ADD1, ADD2, ADD3 and ADD4 can be enabled at any one time. Port 0.7 GPIO 8051 P0.7 GPIO. RXD0 This pin also can be configured as RXD of UART 0. ADD2 P0.7 I/

38、O, A 25 This pin also can be configured as the input to the ADC channel D by setting ANEN of IOCFGP0.7 to 1. Only one of ADD1, ADD2, ADD3 and ADD4 can be enabled at any one time. Port 0.6 GPIO 8051 P0.6 GPIO. TXD0 This pin also can be configured as TXD of UART 0. ADD1 P0.6 I/O, A 26 This pin also ca

39、n be configured as the input to the ADC channel D by setting ANEN of IOCFGP0.6 to 1. Only one of ADD1, ADD2, ADD3 and ADD4 can be enabled at any one time. Port 0.5 GPIO 8051 P0.5 GPIO. PINT1.5 This pin also can be configured as the expanded INT1 interrupt. ADC2 P0.5 I/O, A 27 This pin also can be co

40、nfigured as the input to the ADC channel C by setting ANEN of IOCFGP0.5 to 1. Only one of ADC1 and ADC2 can be enabled at any one time. 86 NIP.oN NIP EPYT EMAN NIP FUNCTION DESCRIPTION Port 0.4 GPIO 8051 P0.4 GPIO. PINT1.4 This pin also can be configured as the expanded INT1 interrupt. ADC1 P0.4 I/O

41、, A 28 This pin also can be configured as the input to the ADC channel C by setting ANEN of IOCFGP0.4 to 1. Only one of ADC1 and ADC2 can be enabled at any one time. Port 0.3 GPIO 8051 P0.3 GPIO. PINT1.3 This pin also can be configured as the expanded INT1 interrupt. ADB2 P0.3 I/O, A 29 This pin als

42、o can be configured as the input to the ADC channel B by setting ANEN of IOCFGP0.3 to 1. Only one of ADB1 and ADB2 can be enabled at any one time. Port 0.2 GPIO 8051 P0.2 GPIO. PINT1.2 This pin also can be configured as the expanded INT1 interrupt. ADB1 P0.2 I/O, A 30 This pin also can be configured

43、 as the input to the ADC channel B by setting ANEN of IOCFGP0.2 to 1. Only one of ADB1 and ADB2 can be enabled at any one time. Port 0.1 GPIO 8051 P0.1 GPIO. PINT1.1 This pin also can be configured as the expanded INT1 interrupt. ADA2 P0.1 I/O, A 31 This pin also can be configured as the input to th

44、e ADC channel A by setting ANEN of IOCFGP0.1 to 1. Only one of ADA1 and ADA2 can be enabled at any one time. Port 0.0 GPIO 8051 P0.0 GPIO. PINT1.0 This pin also can be configured as the expanded INT1 interrupt. ADA1 P0.0 I/O, A 32 This pin also can be configured as the input to the ADC channel A by

45、setting ANEN of IOCFGP0.0 to 1. Only one of ADA1 and ADA2 can be enabled at any one time. VSS Power 33 VSS Internal Regulator Output. 2.25V 2.75V VDD25 Power 34 Typical decoupling capacitors of 0.1uF and 10uF should be connected between VDD25 and VSS. Supply Voltage. 3.0V 5.5V VDD Power 35 A good de

46、coupling capacitor between VDD and VSS pins is critical for good performance. 87 NIP.oN NIP EPYT EMAN NIP FUNCTION DESCRIPTION Reset Low Active. Typically connect a resistor to VDD25 and a capacitor to VSS. Low asserted and threshold at 0.5*VDD25. When forced low, the chip enters into reset conditio

47、n. RSTN I 36 This pin should not be connected to any level above VDD25. Port 4.6 GPIO 8051 P4.6 GPIO. Analog Comparator D Input P4.6 I/O - This pin also can be configured as the positive input of the analog comparator D. Port 2.4 GPIO 8051 P2.4 GPIO. T2EX Timer 2 Trigger This pin also can be configu

48、red as T2EX signal for Timer 2. T2EX is the Timer 2 trigger input. Analog Comparator D Input P2.4 I/O, A 37 This pin also can be configured as the positive input of the analog comparator D. Port 2.5 GPIO 8051 P2.5 GPIO. T2 Timer 2 Input This pin also can be configured as Timer 2 input. Analog Compar

49、ator C Input P2.5 I/O, A 38 This pin also can be configured as the positive input of the analog comparator C. Port 2.6 GPIO 8051 P2.6 GPIO. Analog Comparator B Input P2.6 I/O, A 39 This pin also can be configured as the positive input of the analog comparator B. Port 2.7 GPIO 8051 P2.7 GPIO. Analog Comparator A Input This pin also can be configured as the positive input of the analog comparator A. SWA0 P2.7 I