ID-RP2_serv.pdf

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1、SERVICE MANUAL D-STAR REPEATER SYSTEM S-14205HZ-C1 Nov. 2005 INTRODUCTION This service manual describes the latest service information for the ID-RP2 D-STAR REPEATER SYSTEM at the time of publication. DANGER NEVER connect the transceiver to an AC outlet or to a DC power supply that uses more than 16

2、 V. This will ruin the transceiver. DO NOT expose the transceiver to rain, snow or any liquids. DO NOT reverse the polarities of the power supply when connecting the transceiver. DO NOT apply an RF signal of more than 20 dBm (100 mW) to the antenna connector. This could damage the transceivers front

3、 end. ORDERING PARTS Be sure to include the following four points when ordering replacement parts: 1. 10-Digit Icom parts number 2. Component name and informations 3. Equipment model name and unit name 4. Quantity required 1130009850 S.IC TC74LCX245FT ID-RP2C MAIN UNIT 5 pieces 8810002950 Screw BiH

4、M36 SUS ID-RP2C Cover 10 pieces Addresses are provided on the inside back cover for your convenience. REPAIR NOTES 1. Make sure a problem is internal before disassembling the transceiver. 2. DO NOT open the transceiver until the transceiver is disconnected from its power source. 3. DO NOT force any

5、of the variable components. Turn them slowly and smoothly. 4. DO NOT short any circuits or electronic parts. An insulated tuning tool MUST be used for all adjustments. 5. DO NOT keep power ON for a long time when the transceiver is defective. 6. DO NOT transmit power into a signal generator or a swe

6、ep generator. 7. ALWAYS connect a 50 dB to 60 dB attenuator between the transceiver and a deviation meter or spectrum analyzer when using such test equipment. 8. READ the instructions of test equipment thoroughly before connecting equipment to the transceiver. To upgrade quality, any electrical or m

7、echanical parts and internal circuits are subject to change without notice or obligation. ID-RP2C ID-RP2D ID-RP2V ID-RP2L Icom, Icom Inc. and logo are registered trademarks of Icom Incorporated (Japan) in the United States, the United Kingdom, Germany, France, Spain, Russia and/or other countries. M

8、ODELDESCRIPTION ID-RP2CREPEATER CONTROLLER ID-RP2L 10GHz MICROWAVE LINK REPEATER VersionTX frequencyRX frequency USA10.150-10.175 GHz10.000-10.025 GHz USA-110.000-10.025 GHz10.150-10.175 GHz ID-RP2D1.2 GHz DATA REPEATER ID-RP2V1.2 GHz DIGITAL VOICE REPEATER TABLE OF CONTENTS ID-RP2 SYSTEM CONNECTION

9、 . A ID-RP2C REPEATER CONTROLLER . B ID-RP2L 10GHz MICROWAVE LINK REPEATER . C ID-RP2D 1.2 GHz DATA REPEATER . D ID-RP2V 1.2 GHz DIGITAL VOICE REPEATER . E Antenna filter Duplexer ID-RP2V Coaxial cables (purchase locally) ID-RP2D ID-RP2C A B B A OPC-1380 (supplied w/ID-RP2C) to AH-106/107to AH-106/1

10、07 OPC-1309 (supplied w/ID-RP2D/V) OPC-1309 (supplied w/ID-RP2D/V) Control cable (supplied w/ID-RP2D/V) Control cable (supplied w/ID-RP2D/V) ID-RP2L (Assist 1) AH-108 ID-RP2L (Assist 2) AC outlet AC power cable External DC power supply 13.8 V BlackRed + SYSTEM CONNECTION A SECTION 1 SPECIFICATIONS S

11、ECTION 2 INSIDE VIEW SECTION 3 CIRCUIT DESCRIPITON 3-1 RECEIVER CIRCUITS . B-3-1 3-2 TRNSMITTER CIRCUITS . B-3-1 3-3 POWER SUPPLY CIRCUITS . B-3-1 3-4 OTHER CIRCUITS . B-3-2 SECTION 4 PARTS LIST SECTION 5 MECHANICAL PARTS AND DISASSEMBLY SECTION 6 SEMI-CONDUCTOR INFORMATION SECTION 7 BOARD LAYOUTS 7

12、-1 MAIN UNIT . B-7-1 7-2 LED UNIT . B-7-1 SECTION 8 WIRING DIAGRAM SECTION 9 BLOCK DIAGRAM SECTION 10 VOLTAGE DIAGRAM 10-1 MAIN UNIT . B-10-1 SERVICE MANUAL REPEATER CONTROLLER B faJomO B - 1 - 1 GENERAL Power supply requirement : 13.8 V DC 15% (Negative ground) Current drain : Less than 0.5 A Usabl

13、e temperature range : 10C to +50C; +14F to +122F Dimensions (proj. not included) : 483(W)44(H)257(D) mm; 19(W)134(H)1018(D) in. Weight (Approx.) : 2.7 kg; 5 lb 15 oz Repeater control protocol : Compatible to D-STAR standard LOCAL REPEATER INTERFACE Max. number of connections : 4 Communication speed

14、: Data 128 kbps Voice 4.8 kbps Cable length (approx.) : 3 m; 10 ft (standard; supplied cable of the ID-RP2D/V) ASSIST REPEATER INTERFACE Max. number of connections : 2 Communication speed : Data 10 Mbps Setting CPU communication 19.2 kbps Cable length (approx.) : 30 m; 100 ft (standard; supplied cab

15、le of the ID-RP2L) WIRED INTER FACE Number of connector : 1 Type of connection : 10Base-T MAC address : Unique ID IP address : Programmed with the utility All stated specifi cations are subject to change without notice or obligation. SECTION 1 SPECIFICATIONS ATM-SAR ATM-SAR controllercontroller (IC1

16、6: (IC16: PD98409GN-LMU)PD98409GN-LMU) LVDS recieverLVDS reciever (IC25: SN65LVDT33D)(IC25: SN65LVDT33D) ASSIST I/F FPGAASSIST I/F FPGA (IC19: EP1C6T144C7)(IC19: EP1C6T144C7) LVDS recieverLVDS reciever (IC26: SN65LVDT33D)(IC26: SN65LVDT33D) CPUCPU (IC5: HD6417750SF167)(IC5: HD6417750SF167) SRAMSRAM

17、(IC2, IC3, IC6, IC7(IC2, IC3, IC6, IC7 : : PD444008LLE)PD444008LLE) LOCAL RPT I/F FPGALOCAL RPT I/F FPGA (IC24: EP1C6T144C8)(IC24: EP1C6T144C8) LVDS driverLVDS driver (IC22: SN65LVDS391D)(IC22: SN65LVDS391D) MAIN unitMAIN unit Ethernet controllerEthernet controller (IC8: AM79C973BVD)(IC8: AM79C973BV

18、D) PCI/DMA FPGAPCI/DMA FPGA (IC15: EP1C6Q240C8)(IC15: EP1C6Q240C8) USB-serial controllerUSB-serial controller (IC27: (IC27: IC28: ) IC28: ) Boot ROMBoot ROM (IC12: SC-1408)(IC12: SC-1408) +3.3V regulator+3.3V regulator (IC13: LM2676S-3.3)(IC13: LM2676S-3.3) Flash ROMFlash ROM (IC11: SC-1407)(IC11: S

19、C-1407) LED boardLED board ATM-SAR controller (IC16: PD98409GN-LMU) LVDS reciever (IC25: SN65LVDT33D) ASSIST I/F FPGA (IC19: EP1C6T144C7) LVDS reciever (IC26: SN65LVDT33D) CPU (IC5: HD6417750SF167) SRAMs IC2, IC3, IC6, IC7 : PD444008LLE4 LOCAL RPT I/F FPGA (IC24: EP1C6T144C8) LVDS driver (IC22: SN65

20、LVDS391D) MAIN unit Ethernet controller (IC8: AM79C973BVD) PCI/DMA FPGA (IC15: EP1C6Q240C8) USB-serial controllers (IC27, IC28: FT232BL2) Boot ROM (IC12: SC-1408) +3.3V regulator (IC13: LM2676S-3.3) Flash ROM (IC11: SC-1407) LED unit SECTION 2 INSIDE VIEWS B - 2 - 1 SECTION 3 CIRCUIT DESCRIPTION 3-1

21、 RECEIVED DATA PROCESS 3-1-1 DURING ASSIST REPEATER OPERATION (MAIN UNIT) The demodulated data signal from the connected ASSIST repeater (ID-RP2L) is applied to ASSIST-1 A/B (J13) or ASSIST-2 A/B (J12) connector. The demodulated data sig- nal is applied to the LVDS receivers (IC25, IC26) and con- ve

22、rted to the I/O signal and then applied to the ASSIST I/F FPGA IC (IC19). The ASSIST I/F FPGA IC (IC19) converts the applied I/O signal format to the ATM-SAR interface signal format. The converted ATM-SAR interface signal is applied to the ATM-SAR controller (IC16) and converts the data format into

23、the PCI bus line data format. The converted data signal is applied to the PCI/DMA FPGA IC (IC15). 3-1-2 DURING LOCAL REPEATER OPERATION (MAIN UNIT) The demodulated data signal from the connected LOCAL repeater (ID-RP2D or ID-RP2V) is applied to LOCAL RPT- CONT I/O connector (J10). The applied signal

24、 is amplified at the buffer amplifiers (IC17, IC20, IC21, IC23) and then applied to the LOCAL RPT I/F FPGA IC (IC24). The LOCAL RPT I/F FPGA (IC24) detects header frame synchronization and then converts the format into the serial data signal. The converted serial data signal is applied to the PCI/DM

25、A FPGA IC (IC15). 3-1-3 DURING CONNECTED SERVER OPERATION (MAIN UNIT) The data signal from the connected server is applied to the 10BASE-T connector (J1) and then applied to the Ethernet controller (IC8). The Ethernet controller (IC8) converts the data format into the PCI bus line data format. The c

26、onverted signal is applied to the PCI/DMA FPGA IC (IC15). 3-1-4 SRAM CIRCUIT (MAIN UNIT) The PCI/DMA FPGA IC bridges the data signal from the ATM-SAR controller (IC16), LOCAL RPT I/F FPGA (IC24) or Ethernet controller (IC8) to the SRAM circuit. The bridged data signal from the PCI/DMA FPGA IC (IC15)

27、 is applied to the SRAM circuit (IC2, IC3, IC6, IC7) and then memorized for transmission. The bridged data signal from the PCI/DMA FPGA IC (IC15) is also applied to the CPU (IC5) and the CPU analyzes the call sign settings. The CPU (IC5) selects the desired repeater or connected server for transmiss

28、ion according to the analyzed call sign settings. 3-2 TRANSMIT DATA PROCESS 3-2-1 SRAM CIRCUIT (MAIN UNIT) The memorized data from the SRAM circuit is transferred to the desired repeaters or connected server at the PCI/DMA FPGA IC according to the analyzed call sign settings at the CPU. The data sig

29、nal from the SRAM circuit (IC2, IC3, IC6, IC7) is applied to the PCI/DMA FPGA IC (IC15) and the PCI/ DMA FPGA IC (IC15) selects one of the ATM-SAR control- ler (IC16), LOCAL RPT I/F FPGA (IC24) or Ethernet con- troller (IC8) by the CPU (IC5). B - 3 - 1 IC17, IC20, IC21, IC23IC24 IC15 IC5 Buffer ampl

30、ifier ID-RP2D/ ID-RP2V ID-RP2L ID-RP2C LOCAL RPT I/F FPGA PCI/DMA FPGA CPU SRAM IC2, IC3, IC6, IC7 IC22 IC19 LOCAL REPEATER ASSIST REPEATER IC16 LVDS driver IC25, IC26 LVDS receiver ASSIST I/F FPGA ATM-SAR controller Ethernet controller IC8 10BASE-T Gateway Server etc. LOCAL BUS PCI BUS REPEATER CON

31、TROL CIRCUIT 3-4 OTHER CIRCUITS REPEATER CONTROL CIRCUITS (MAIN UNIT) The repeater control circuits consist of the CPU (IC5), Boot ROM (IC12), Flash ROM (IC11), SRAM (IC2, IC3, IC6, IC7). A 32-bit processor is adopted as the CPU (IC5), and the 22 MHz signal, generated by the clock oscillator (X2), i

32、s used for the CPU clock after being multiplied by 6 at the inside the CPU. The Boot ROM (IC12) is 16 M-bit flash memory as 8 bits each. The Flash ROM (IC11) is 32 M-bit flash memory as 16 bits each. The SRAM circuit (IC2, IC3, IC6, IC7) contains four 4 M-bit SRAM IC as 32 bits each. 33 MHz CLOCK CI

33、RCUIT (MAIN UNIT) The 22 MHz clock signal is multiplied by 3/2 at the inside of the CPU (IC5) and then amplified at the clock driver (IC15). The amplified clock signal is applied to the PCI/DMA FPGA IC (IC15), Ethernet controller (IC8), ATM-SAR controller (IC16). USB CONTROLLER (MAIN UNIT) While set

34、ting the ASSIST repeater (ID-RP2L), the USB con- trollers are used for communication with the connected PC. While reading the setting data from the connected ASSIST repeater (ID-RP2L), the setting data is applied to the LVDS receivers (IC25, IC26) in the differential data format. The applied data fo

35、rmat is converted into the serial data format at the LVDS receivers (IC25, IC26). The converted serial data is applied to the USB controllers (IC27, IC28) to be converted into the USB data format. The converted USB data is applied to the connected PC via SERVICE 1 (J19) or SERVICE 2 (J20) connector.

36、 While writing the setting data to the connected ASSIST repeater (ID-RP2L), the setting data is applied to the USB controllers (IC25, IC26) via SERVICE 1 (J19) or SERVICE 2 (J20) connector. The USB controllers (IC25, IC26) con- vert the applied data format into the serial data format. The converted

37、serial data is applied to the LVDS driver (IC22) and converted into the differential data format. The con- verted differential data is applied to the connected ASSIST repeater (ID-RP2L). B - 3 - 2 3-3 POWER SUPPLY CIRCUITS LineDescription 3.3 V Common 3.3 V converted from the 13.8 V line by the 3.3

38、V regulator circuit (IC13). The output voltage is applied to the SRAM ICs (IC2, IC3, IC6, IC7), ATM-SAR controller (IC16), etc. 1.8 V Common 1.8 V converted from the 3.3 V line by the 1.8 V regulator circuit (IC33). The output voltage is applied to the CPU (IC5). 1.5 V Common 1.5 V converted from th

39、e 3.3 V line by the 1.5 V regulator circuit (IC34). The output voltage is applied to the ASSIST IF FPGA IC (IC19), LOCAL RPT I/F FPGA IC (IC24), etc. 3-2-2 DURING ASSIST REPEATER OPERATION (MAIN UNIT) The data signal from the PCI/DMA FPGA IC (IC15) is applied to the ATM-SAR controller (IC16) and con

40、verts the signal format into the ATM-SAR interface signal format. The converted interface signal is applied to the ASSIST I/F FPGA IC (IC19) to convert the signal format into the I/O sig- nal format . The converted I/O signal is applied to the LVDS driver (IC22) and converts the I/O signal format in

41、to the dif- ferential signal format. The differential signal is applied to the connected ASSIST repeater (ID-RP2L) via ASSIST-1 A/B (J13) or ASSIST-2 A/B (J12) connector. 3-2-3 DURING LOCAL REPEATER OPERATION (MAIN UNIT) The data signal from the PCI/DMA FPGA IC (IC15) is applied to the LOCAL RPT I/F

42、 FPGA IC (IC24) and converts the signal format into the parallel data signal format. The converted parallel data signal is applied to the buf- fer amplifiers (IC17, IC20, IC21, IC23) and then applied to the connected LOCAL repeater (ID-RP2D or ID-RP2V) via LOCAL RPT CONT I/O connector (J10). 3-2-4 D

43、URING CONNECTED SERVER OPERATION (MAIN UNIT) The data signal from the PCI/DMA FPGA IC (IC15) is applied to the Ethernet controller (IC8) and converts the data format into the Ethernet data format. The converted Ethernet data is applied to the connected server via 10BASE-T connector (J1). B - 4 - 1 S

44、ECTION 4 PARTS LIST M.=Mounted side (T: Mounted on the Top side, B: Mounted on the Bottom side) REF ORDER DESCRIPTION M. H/V NO. NO. LOCATION MAIN UNIT IC1 1130009850 S.IC TC74LCX245FT (EL) T 65.5/166.5 IC2 1130011731 S.IC PD444008LLE-A12 T 155/140.5 IC3 1130011731 S.IC PD444008LLE-A12 T 181/140.5 I

45、C4 1130011360 S.IC HD74LVC14TELL T 65.5/188.5 IC5 1140011870 S.IC HD6417750SF167 T 100/164.5 IC6 1130011731 S.IC PD444008LLE-A12 T 155/114.5 IC7 1130011731 S.IC PD444008LLE-A12 T 181/114.5 IC8 1130012730 S.IC AM79C973BVDW T 29/76.5 IC9 1130007030 S.IC TC7W08FU (TE12L) T 65.5/178 IC10 1120002990 S.IC

46、 MAX3232CSE T 108.5/210 IC11 1130012300 S.IC MBM29LV320TE-90TN/SC-1407 T 159.5/86 IC12 1130012310 S.IC MBM29LV160TE90TN/SC-1408 T 160.3/62.5 IC13 6910015300 S.DC LM2676S-3.3 T 190/42.5 IC14 1130012330 S.IC EPCS1SI8 / SC-1409 T 89/120.3 IC15 1130011710 S.IC EP1C6Q240C8 T 88.5/87 IC16 1130011420 S.IC PD98409GN-LMU T 33/1